CHERI webinar banner
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3917
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3917
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

An Update on Calibre at DAC

An Update on Calibre at DAC
by Daniel Payne on 06-09-2014 at 12:00 pm

Even though I live just 7 miles away from the Mentor Graphics corporate office in Oregon, I visited their DAC suite in San Francisco last week to get an update on Calibrefrom Michael White. The Calibre tools are used during IC verification and sign-off by performing DRC (Design Rule Checking) and LVS (Layout Versus Schematic).


Trends – there is double patterning starting at the 20nm node which requires lots more computation for mask making. The 10nm node is being working on right now.

FinFET – being used at 16nm and 14nm nodes, and has some new fill requirements. A field solver is needed for 3D extraction of parasitics on FinFET devices. DRC gets more complex, with added checks. Equation-based DRC is useful here as well.

10nm – foundries working on this node now, so multi-patterning requirement continues beyond just Double Patterning Technology (DPT).

FinFET devices are more challenging for IC design, layout, extraction and physical verification. The Calibre xACT 3Dtool is a 3D field solver used on FinFET devices, like the TSMC 16nm process.

SmartFill is used on 20nm and 16nm nodes to be FinFET-aware, improves silicon yield. Real time density checking in a single pass, instead of iterative passes. Qualified at both Samsung and TSMC fabs.

At 10nm there are new checks for density balancing. Engineering goal is to improve Calibre run time performance by adding more CPUs. Going from 250nm down to 20nm designs there is a 3,500X increase in computation required for DRC and LVS runs.

Over the past 6 months the run-time performance has improved some 40% due to incremental improvements in Calibre.

Multiple voltage domains bring new requirements, like voltage-based design rules, so there’s a Calibre flow for that.

Concept of auto-waivers is now supported, so that reduces the amount of false errors to review when you run the full chip DRC. You can automatically send the waivers to the foundry for approval.

Pattern Matching is a technique to easily capture the complex 2D relationships for analysis, filtering, waiving, etc. Uses for pattern matching include: DFM (Design for Manufacturing), LFD (Litho Friendly Design), OPC (Optical Proximity Correction), FA (Failure Analysis).

Multi-patterning is used at 20nm and lower nodes, qualified as the standard at TSMC, etc. Samsung and GLOBALFOUNDRIES support the concept of stitching to fix the coloring requirement.

3D stacking verification is supported using 3DStack and the xACT-TSV tool. Silicon Photonics is a newer area for high-speed communications, using curved layout structures and Calibre can verify these layouts.

Foundries all use Calibre internally: TSMC, Samsung, GLOBALFOUNDRIES.

Even Intel is using Calibre on their FinFETs at 22nm and 14nm.

At 10nm even TSMC will have to use coloring, expect triple and quad patterning. Fill becomes more complex at 10nm, layout is colored, then fill adjacent is the opposite color. Space Assisted Double Patterning (SADP) required by one foundry. Early Calibre decks available at 10nm for TSMC, Samsung, GF, IDM.

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.