Tag: cadence

Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus

Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
by Daniel Nenni on 10-12-2022 at 10:00 am
Categories: Uncategorized

Dan is joined by Brandon Bautz, Sr. Group Director of Product Management, responsible for the Cadence silicon signoff and verification product lines in the Digital & Signoff Group.

Dan and Brandon explore the substantial challenges faced by design teams needing to perform full-chip signoff at an accelerated pace for advanced… Read More

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Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC

Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
by Daniel Nenni on 09-20-2022 at 10:00 am
Categories: Ansys, Inc., Chiplet, EDA

Ansys chip package board

Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More

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Samsung Foundry Forum & SAFE™ Forum 2022

Samsung Foundry Forum & SAFE™ Forum 2022
by Daniel Nenni on 09-16-2022 at 6:00 am
Categories: Events, Foundries, Samsung Foundry

SFF SAFE GLOBAL Banner 400 400

It has been an exciting time in the semiconductor industry and the excitement is far from over. Years 2022 and 2023 will be more challenging in many different ways and live activities have just begun. The cornerstones to the semiconductor industry are the foundries so I look forward to the live foundry events coming up in October,… Read More

Podcast EP105: Cadence STA Strategy and Capabilities, Today and Tomorrow with Brandon Bautz

Podcast EP105: Cadence STA Strategy and Capabilities, Today and Tomorrow with Brandon Bautz
by Daniel Nenni on 09-02-2022 at 10:00 am
Categories: Uncategorized

Dan is joined by Brandon Bautz, senior group director of product management responsible for silicon signoff and verification product lines in the Cadence Digital & Signoff Group. Brandon has more than 20 years of experience in chip design and the EDA industry and has been at Cadence for over 10 years.

Dan explores the current… Read More

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Unlock first-time-right complex photonic integrated circuits

Unlock first-time-right complex photonic integrated circuits
by Raha Vafaei on 06-01-2022 at 10:00 am
Categories: Ansys, Inc., EDA, Events

EPDA overview

The capacity and energy efficiency challenges from the growing appetite for high-speed data along with advanced applications such as LIDAR and quantum computing are driving demand for increasingly large-scale photonic integrated circuits (PIC). With an ever-increasing number of components on a single photonic chip, manual… Read More

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Designing Ultra-Low-Power, Always On IP

Designing Ultra-Low-Power, Always On IP
by Daniel Payne on 05-09-2022 at 10:00 am
Categories: Cadence, Events, IP

processor and sensor trends min

It’s popular to use DSP chips for vision processing in diverse applications like ADAS, security cameras and AR. Tensilica has been designing DSP chips and IP since 1997, and their technology was successful enough that Cadence acquired Tensilica back in 2013. At the IP-SoC Silicon Valley 2022 event in April I had the pleasure… Read More

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Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%

Design IP Sales Grew 19.4% in 2021, confirm 2016-2021 CAGR of 9.8%
by Eric Esteve on 05-05-2022 at 6:00 am
Categories: Alphawave Semi, Arm, Cadence, IP, IPnest, Semiconductor Services, Synopsys

Table IP 2020 2021 1

Design IP Sales reached $5.45B in 2021, or 19.4% YoY after 16% in 2020, on-sync with semiconductor growth of 26.2% in 2021 according to WSTS. IPnest has released the “Design IP Report” in May 2022, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O,… Read More

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Cadence and DesignCon – Workflows and SI/PI Analysis

Cadence and DesignCon – Workflows and SI/PI Analysis
by Daniel Nenni on 04-02-2022 at 6:00 am
Categories: Cadence, EDA, Events

Clarity 3D solver 112Gbps

DesignCon 2022 is back to a live conference, from Tuesday, April 5th through Thursday, April 7th, at the Santa Clara Convention Center.

Introduction

DesignCon is a unique gathering in our industry.  Its roots incorporated a focus on complex design and analysis requirements of (long-reach) high-speed interfaces.  Technical… Read More

Podcast EP67: Corigine Combines Emulation and Prototyping

Podcast EP67: Corigine Combines Emulation and Prototyping
by Daniel Nenni on 03-18-2022 at 10:00 am
Categories: Uncategorized

Dan is joined by Jeff Critten, VP of sales at Corigine. They discuss the unique capabilities of Corigine that allows support of both emulation and prototyping in one platform.

Jeff Critten has been in the EDA industy for over 25yrs.  He started with Cadence as a verification AE in 1997 and moved into a sales role where he was promoted… Read More

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Leveraging Virtual Platforms to Shift-Left Software Development and System Verification

Leveraging Virtual Platforms to Shift-Left Software Development and System Verification
by Kalar Rajendiran on 03-15-2022 at 6:00 am
Categories: Cadence, EDA, Events, IP

Extend Accuracy with Hybrid Platforms

Ever since the cost of development started growing exponentially, engineering teams have been deploying a shift-left strategy to software development and system verification. While this has helped contain cost and accelerated product development schedules, a shift-left strategy is not without challenges. A virtual platform… Read More