Date and time: February 2, 2024 (Friday) 13:00-14:40
Sponsor:
Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters
Cost: Free
Venue: Online (Zoom webinar)
*You can also participate from a web browser.
We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: February 1st (Thursday)… Read More
Date and time: January 30, 2024 (Tuesday) 13:00-14:20
Sponsor:
Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters
Cost: Free
Venue: Online (Zoom webinar)
*You can also participate from a web browser.
We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: January 29th (Monday)… Read More
The heterogeneous integration of chips/chiplets has added significant complexity to the IC package design process, further compressing schedules for many design teams. Design teams must work more efficiently to meet quality and performance goals while maintaining schedule milestones.
One way to improve efficiency is to… Read More
In my previous article, we touched on ways to pull in the schedule. This time I’d like to analyze how peak usage affects project timeline and cost. The above graph is based on real pattern taken from one development week in Annapurna Labs 5nm Graviton.
The Graph shows the number of variable servers per hour per day. There’s a baseline… Read More
Whether you’re a beginner or a seasoned engineer, this webinar is a must-watch for anyone in the electronic design space. Join us to discuss how you can accelerate your PCB design process with our new and improved OrCAD X layout environment.
My beautiful wife and I attended the annual Global Semiconductor Alliance (GSA) Awards event last week. Usually this is a solo event but since my wife is CFO of SemiWiki I was able to get her an invite. I go every year and she wanted to see what all of the excitement was about. She also knows quite a few industry people from attending the… Read More
In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator,… Read More
Date and time: Friday, December 8, 2023 14:00-15:00
Sponsor: Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters
Cost: Free
Venue: Online (Zoom webinar)
*You can also participate from a web browser. We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: December 7th (Thursday)… Read More
