Cadence Mixed Signal Technology Forum

Cadence Mixed Signal Technology Forum
by Paul McLellan on 10-29-2014 at 7:00 am

Yesterday was Cadence’s annual mixed-signal technology forum. I think that there was a definite theme running through many of the presentations, namely that wireless communication of one kind or another is on a sharp rise with more and more devices needing to connect to WiFi, Bluetooth and so on. This was most obvious during… Read More


How ST Designs with Layout Dependent Effects (LDE)

How ST Designs with Layout Dependent Effects (LDE)
by Daniel Payne on 10-15-2014 at 12:00 am

I first visited STat their Agrate, Italy site where Flash memory development is done. At DACthis year Antonio Bogani talked about how ST designs with LDE while using EDA tools and a PDK (Process Design Kit) from Cadence. They recorded the 17 minute presentation, and you can view it herewithout having to register. Antonio’s… Read More


TSMC ♥ Cadence!

TSMC ♥ Cadence!
by Daniel Nenni on 10-11-2014 at 4:30 pm

One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.

Of late,… Read More


Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom … Read More


AMD Design IP Deal with Virage Logic… Oops… Synopsys

AMD Design IP Deal with Virage Logic… Oops… Synopsys
by Eric Esteve on 09-23-2014 at 9:59 am

Whoever has said that history never repeats itself should read this recent PR from AMD! The news can be summarized in three points:

  • Multi-year agreement gives AMD access to a range of Synopsys design IP including interface, memory compiler, logic library and analog IP for advanced FinFET process nodes
  • Synopsys acquires rights
Read More

Samsung 14nm FinFET Design with Cadence Tools

Samsung 14nm FinFET Design with Cadence Tools
by Daniel Payne on 09-22-2014 at 5:30 pm

The first consumer products with 20nm processing are arriving in 2014 like the 2 billion transistor A8 chip in the iPhone 6, however at the 14nm node there are new designs underway to continue the trend of Moore’s Law. To get a better feel for the challenges of designing with 14nm FinFET technology I watched a 23 minute video … Read More


MEMS+, Bringing MEMS into the Electronic World

MEMS+, Bringing MEMS into the Electronic World
by Paul McLellan on 09-19-2014 at 1:59 pm

One of the things about MEMS devices is that they almost always live on a chip that also contains the electronics necessary to process the output from the sensor. For example, an on-chip accelerometer for a car airbag deployment will contain the electronics necessary to process the signal from the sensor and end up with something… Read More


Expert Tool to View and Debug Design Issues at Spice Level

Expert Tool to View and Debug Design Issues at Spice Level
by Pawan Fangaria on 09-12-2014 at 7:00 am

Spice view of a design, block or fragment of the design is probably the lowest level of functional description of a circuit in terms of transistors, resistors, capacitors, interconnect and so on, which in several ways acts as an ultimate proof of pudding for any semiconductor design before manufacturing. However, it’s generally… Read More


SmartScan Addresses Test Challenges of SoCs

SmartScan Addresses Test Challenges of SoCs
by Pawan Fangaria on 09-04-2014 at 4:00 pm

With advancement of semiconductor technologies, ever increasing sizes of SoCs bank on higher densities of design rather than giving any leeway towards increasing chip area and package sizes; a phenomenon often overlooked. The result is – larger designs with lesser number of pins bonded out of ever shrinking package sizes;… Read More


Cadence and Reverse Debugging

Cadence and Reverse Debugging
by Paul McLellan on 08-22-2014 at 7:01 am

I wrote back in March about Undo Software. They have a reverse debugging solution called UndoDB (the DB is for debug, not database). I have a soft spot for reverse debugging ever since seeing one of the engineers at Virtutech type reverse single step and seeing the code back up a single instruction and realizing that literally months… Read More