A Methodology for Assertion Reuse in SoC Designs

A Methodology for Assertion Reuse in SoC Designs
by Daniel Payne on 02-21-2014 at 4:24 pm

As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to … Read More