At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.
As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult… Read More
At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.
On December 15[SUP]th[/SUP] I had the opportunity … Read More
In the first four installments of this series we have examined Moore’s law, described the drivers that have enabled Moore’s law and discussed the specific status and issues around DRAM and logic. In this final installment we will examine NAND Flash.… Read More
The Applied Materials earnings call was last week. As usual I”m not all that interested in the financial details of the quarter and I’m certainly not the person to pick whether the stock is going to go up or down in the immediate future. However, there is always interesting information to be gleaned from the semiconductor… Read More
I spent all of last week at SEMICON West meeting with customers, potential customers, partners and various industry analysts and experts. I was involved in many interesting discussions over the course of the week and I thought I would share some of the more interesting observations:
Alternate Fin Materials Pushed Out
I have for… Read More