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IC Mask SemiWiki Webinar Banner 
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IC Mask Design
Posted on by Daniel Nenni

WEBINAR: FinFET UltraPcell Methodology

WEBINAR: FinFET UltraPcell Methodology
by Daniel Nenni on 05-25-2023 at 6:00 am
Categories: Events, FinFET, IC Mask Design, Semiconductor Services

ICMask PG Pcells JUNE Webinar

The custom physical implementation of circuit designs is a critical component of the integrated circuit (IC) process. Unfortunately, this step has been known to be one of the most time-consuming and prone to human error. Therefore, the need for a methodology that allows for faster, more accurate, and less error-prone work is evident. At IC Mask Design, we set out to find a way to implement such a methodology using the same tools we currently use without any extra code.

In this webinar, we present an elegant and straightforward solution that utilizes Ultra PCells, focusing on FinFET technologies. The concept is simple: design tiles, or bed frames, which can be used to floorplan and provide the flexibility to add connections within the tile, switch them on or off as needed, and adjust the density. This approach allows teams to work in a more cohesive manner since everyone uses the same tiles, making integration easy. It also enables teams to complete tasks more quickly, thereby allowing for more floorplans, post-layout simulation fixes, and area estimations to be completed with more accuracy from the very beginning.

Our methodology offers several key advantages. Firstly, it allows for greater control over the IC design process, which results in fewer errors and less wasted time. Secondly, it provides a clear framework for teamwork, allowing multiple designers to work simultaneously without stepping on each other’s toes. Thirdly, it is an efficient approach that does not require additional software or coding expertise, saving valuable time and resources. Finally, it is an adaptable methodology that can be customized to suit a wide range of design needs.

In summary, our new methodology utilizing Ultra PCells and bed frames for floor planning and integration offers a simple, elegant, and effective solution to a longstanding problem in the IC design process. It allows for faster and more accurate work, enables teams to work cohesively, provides greater control over the design process, and is an adaptable methodology that can be customized to suit different design needs.

Register Here
Abstract
This webinar looks at the challenges of one of the main tasks a layout engineer has i.e., making a floorplan. Making a floorplan is one of the main tasks that a layout engineer has, the implementation of the floorplan will directly affect different variables:
• Area
• Matching of devices
• Density of base layers Although these are the main and more tangible variants that the floorplan affects, there are some others that will affect the quality and efficiency of the physical implementation of the circuit
• Power Structure
• Routing area
• Schedule With the “Power Aware Floor planning” methodology we will be able to have a good understanding of our power structure from the beginning for both Analog and Digital Blocks
In the case of only digital Blocks, with this methodology, an Engineer can make good quality layout, fast, easy, and even save area compared to circuits provided by the foundries.
Speaker
IC Mask Design Technical Lead, Jorge Araiza, originates from Mexico and has over 7 years of experience working as an Analog Layout engineer, mainly in FinFET technologies. Jorge’s presentation is titled: “Power (Source) Aware Floorplan” and looks at the challenges of one of the main tasks a layout engineer has i.e., making a floorplan.
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