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ARM TechCon 2011 Trip Report and Sailing Semiconductors!

ARM TechCon 2011 Trip Report and Sailing Semiconductors!
by Daniel Nenni on 10-26-2011 at 9:37 pm
Categories: Arm, Cadence, IP, Siemens EDA, TSMC

This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat which is currently in Mexico for the Winter. I’ve sailed on the Esmeralda before but she has just been sold so this was a momentous occasion. Uncle Jim has some health issues so he will be a land locked for the rest of his days. Sailing up and down the Coast is very hard work, believe it!

On the semiconductor side, sailing has come a long way since Esmeralda was first launched. The marine electronics available today are amazing and the ability to run those low-power semiconductor devices via the wind and sun is simply incredible. There should be an ARM Inside sticker on every sailboat! Even the shower is 100% solar and let me tell you that water gets hot! Esmeralda can also desalinate saltwater faster than we could drink it! As the picture suggests we were 3G enabled so, yes, I sailed the internet! Uncle Jim did his best to keep Esmeralda up to date but now technology moves much faster than he can.

I chose Tuesday for ARM TechCon to see the keynotes by TSMC’s Dr. Shang-Yi Chiang, my favorite EDA CEO Dr. Wally Rhines, and Cadence Sr VP Dr. Chi-Ping Hsu. Somebody from the conference called me tonight (Wednesday) and asked why I didn’t attend. Well, you gave me a one-day pass that’s why! But seriously, why the strong ARM tactic? The place was jam PACKED with semiconductor professionals. Having 99.99% market share must be nice!

Shang-Yi’s presentation was similar to the one at OIP last week which I blogged about HERE. According to Shang-Yi, the biggest problems to face the semiconductor industry in the years to come will be more economic than technical, citing the increasing costs of wafers as geometry decreases and density increases. He also stated that FinFets will keep semiconductors scaling through the 14nm and 7nm nodes. I certainly hope he is right. I have 4 kids to put through college.

Wally’s presentation was again by far the best. I expected a rehashed version of his OIP speech, “Accelerating Innovation Through Collaboration” which I blogged about HERE, but no, he pulled out another excellent presentation, “Creating Measurable Value Through Differentiation”. Every CEO in the semiconductor ecosystem should memorize this one! Why have I not seen any press on this? SemiWiki blogger Dr. Paul McLellanwill did a more thorough blog on it HERE.

Chi-Ping’s presentation was the biggest disappointment, I actually walked out. I know Chi-Ping from the Avanti days and can tell you that material did not come from him. Cadence marketing people clearly possessed him with infomercials and all! He even mentioned EDA360!?!?!? Richard Goering’s blog on it, “ARM TechCon Address: High Stakes at Low Process Nodes” was much better than the presentation itself.

ARM did not feed the media but thankfully Jim Lai, President of Global Unichip, invited me to lunch so I did not starve. I will blog about our lunch conversation this weekend but let me tell you this, the semiconductor design ecosystem is about to change once again!

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TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report

TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report
by Daniel Nenni on 10-23-2011 at 3:00 pm
Categories: EDA, Foundries, TSMC

The TSMC OIP conference was Monday and Tuesday of last week. You have probably NOT read about it since it was invitation only and press was not invited. Slides were not made available (except for Mentor), no photos or video were allowed, it was a very private affair. Given that, I won’t be able to go into great detail but I will give you the impression it left on me and I will share slides from the best vendor presentation given on the second day.

TSMC OIP day 1 was for ecosystem partners (EDA, IP, Design Services) and I would say there were about 200 of us. My badge was courtesy ofSolido Design (I do the foundry work for Solido). Presentations were made by Cliff Hou, Vice President of Design Enablement, and LC Lou, Senior Director of IP Development and a couple of other TSMC guys that I did not know. I have worked with both Cliff and LC over the years and have a great respect and trust for them.

28nm and 20nm were discussed in great detail in regards to design enablement and IP. It was very clear that TSMC is finished with 28nm which ramped 3 times faster than 40nm. All 28nm process nodes: 28HP, 28HPL, 28LP and 28HPM (M=mobile) are in production with thousands of wafers already shipped to customers. This tracks with what I have heard from TSMC’s top customers, 28nm silicon is out and working. The first 20nm production wafers are scheduled for mid 2012. This also tracks with what customers have told me, who are finishing up 20nm PDKS in time for Christmas.

The technical deep dive was on RDRs (restricted design rules) which are new in 28nm. TSMC said it took customers about a month to adjust to RDRs which may be a little optimistic. The 28nm DRM (design rule manual) is significantly larger than 40nm, meaning the rules are more difficult to describe. Feedback I got from customers however was that RDRs made their life easier and without RDRs 28nm would not have yielded well at all.

3D IC was discussed in great detail which is a blog in itself. The takeaway here is that TSMC is leading the way in 3D IC, believe it. The other interesting topic was LDEs (layout dependent effects). New effects are coming at 20nm so you can bet LDE will be a big part of the next round of TSMC reference flows (13.0) you will see at the 2012 Design Automation Conference in San Francisco. These reference flows will probably be at 20nm since DAC is mid 2012, same as TSMC 20nm availability. Early access to process technology by both partners and customers was mentioned throughout the two days and I can tell you TSMC is doing much better with early access than other foundries, which was a clear differentiator for the top fabless companies at 28nm.

Day 2 was for customers which I would guess was close to a thousand people. Rick Cassidy, President of TSMC North America, did the keynote. Side note: Rick is a West Point graduate which may explain his no nonsense speaking style. Shang-Yi was next then Cliff Hou. The hot topic here was FinFets. I have blogged about this before but the message that day was FinFets would have delayed 20nm so TSMC stuck with planar transistors. The FinFet design ecosystem challenge was discussed (3D extraxtion, modeling, etc…) and TSMC flat out asked customers if they wanted FinFets for 14nm (2015). The customers I talked to will look at the technical versus time-to-market trade-offs of FinFets which is still being calculated.

Vendor presentations were next from Mike Inglis (ARM), Aart de Geus (Synopsys), Lip-bu Tan (Cadence), and Wally Rhines (Mentor). Mentor was the only vendor “open enough” to send me slides so that is the only presentation I will mention. According to Wally 28/20nm will be a “Golden Era” for foundries. Massive capital investment by foundries will yield (pun intended) very cost effective wafers that will absorb existing products at the higher nodes. 28/20nm cost and capability will also drive new applications and accelerate semiconductor industry growth for years to come. Absolfreakinlutely!

Wally’s presentation has 45 slides and several important points which should be independent blogs. His last slide is my favorite however, it is his personal collaboration ecosystem. My personal collaboration ecosystem is much larger of course since it includes all of you.

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Mentor at the TSMC Open Innovation Platform Ecosystem Forum

Mentor at the TSMC Open Innovation Platform Ecosystem Forum
by Daniel Payne on 10-17-2011 at 3:14 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

Tomorrow in San Jose you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

Here are some of the topics that will interest IC designers using Mentor tools:

iLVS: Accessible, Supportable Paradigm for Circuit Verification at Advanced Nodes (2:30PM, EDA Track)
Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. The number of layers and layer derivations are increasing and the complexity of devices, especially Layout Dependent Effects (LDS), becomes harder and harder to model. In the past, customers could take a foundry rule deck and easily modify it to include their own device models for transistors, resistor, capacitors, inductors, etc., and even augment the deck with their own checks. At 40nm, 28nm, few customers are able to do this confidently. To address this situation, TSMC and Mentor Graphics will discuss how they collaborated to define iLVS, a syntax that provides customers with a more easily adaptable solution to their circuit verification needs. Using iLVS, users can more easily modify and augment foundry rule decks, yet still adhere to the modeling and manufacturing intent captured in these decks.

Keys to Successful DFM Partnership (4:00PM,IP/EDA/Services Track)
DFM is now a known necessity for advanced nodes. But a successful DFM strategy is more than a “push button” solution. It depends on a synergistic combination of tool technology and design methodology, and close collaboration with the foundry. In this session, CSR and Mentor will relate their personal experiences with DFM, its implementation in the TSMC ecosystem, discuss critical factors that determine the difference between success and failure in actual practice.

Challenges and Directions for Next Generation 3D-IC (4:30PM, EDA Track)
The IC industry is steadily moving to the third dimension of scaling, i.e., stacking die vertically using through silicon vias (TSVs) to make inter-die connections in a manner analogous to copper vias in multi-layer printed circuit boards (PCBs), but on a much smaller scale. The 2.5D interposer solution is here today, but next generation, ergo full 3D, will bring additional complexities. For example, when TSVs are introduced into the active area of an IC, things get complicated due to complex electrical, mechanical stress and thermal interactions that impact circuit performance and reliability. In this session Qualcomm and Mentor Graphics will discuss some of the challenges of designing 3D-ICs and what the ecosystem is doing to provide the needed methods and tools to make next generation 3D-IC a reality.

Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes (5:00PM,IP/EDA/Services Track)
Preventing electrical circuit failure is a growing concern for IC designers today. For certain types of failures such as Electrostatic discharge (ESD) issues, there are well established best practices and design rules that circuit designers should be adhering to. Other issues are more recent, such as the best way to design circuits that cross different voltage regions on a chip. While these topics are not unique to a specific technology node, in particular for analog mixed signal they become increasingly critical as the oxides get thinner for the most advanced nodes and as circuit designers continue to put more and more voltage regions on-chip. To validate that circuits have robust protection from electrical failure, TSMC and MGC will present how they have partnered to define and develop rule decks that enable automatic advanced circuit verification to address these issues at the 28nm and 40nm nodes.

Information on the TSMC Open Innovation Platform Ecosystem Forum is here.

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TSMC Gets Fooled Again!

TSMC Gets Fooled Again!
by Daniel Nenni on 10-16-2011 at 2:51 pm
Categories: Foundries, TSMC

If you follow the SemiWiki Twitter feed you may have noticed that The Motley Fool (Seth Jayson) did three more articles on TSMC financials. The first Foolish article was blogged on SemiWiki as “TSMC Financial Status and OIP Update”.

The next three Fool Hardy articles look at cash flow (the cash moving in and out of a business), accounts receivable (AR), days sales outstanding (DSO) and a closer look at margins. All three articles are interesting reads so if you have the time I would definitely click over. If not, here are the cool pictures and my expert guess of the foundry business going forward.
Don’t Get Too Worked Up Over #TSMCEarnings http://www.fool.com/investing/general/2011/10/04/dont-get-too-worked-up-over-taiwan-semiconductor-.aspx

Over the past 12 months, Taiwan Semiconductor Manufacturing generated $687.4 million cash while it booked net income of $5,543.0 million. That means it turned 4.5% of its revenue into FCF (Free Cash Flow). That sounds OK.

However, FCF is less than net income. Ideally, we’d like to see the opposite. Since a single-company snapshot doesn’t offer much context, it always pays to compare that figure to sector and industry peers and competitors, to see how your business stacks up.

With questionable cash flows amounting to only -1.1% of operating cash flow, Taiwan Semiconductor Manufacturing’s cash flows look clean. Within the questionable cash flow figure plotted in the TTM period above, changes in taxes payable provided the biggest boost, at 1% of cash flow from operations. Overall, the biggest drag on FCF came from capital expenditures, which consumed 92.2% of cash from operations.

DanielNenni SemiWiki.com
#TSMCPasses This Key Test fool.com/investing/gene…

Sometimes, problems with AR or DSO simply indicate a change in the business (like an acquisition), or lax collections. However, AR that grows more quickly than revenue, or ballooning DSO, can also suggest a desperate company that’s trying to boost sales by giving its customers overly generous payment terms. Alternately, it can indicate that the company sprinted to book a load of sales at the end of the quarter, like used-car dealers on the 29th of the month. (Sometimes, companies do both.)

Why might an upstanding firm like Taiwan Semiconductor Manufacturing do this? For the same reason any other company might: to make the numbers. Investors don’t like revenue shortfalls, and employees don’t like reporting them to their superiors.

Is Taiwan Semiconductor Manufacturing sending any potential warning signs? Take a look at the chart above, which plots revenue growth against AR growth, and DSO. Will Taiwan Semiconductor Manufacturing miss its numbers in the next quarter or two? I don’t think so. AR and DSO look healthy. For the last fully reported fiscal quarter, Taiwan Semiconductor Manufacturing’s year-over-year revenue grew 5.3%, and its AR dropped 3.9%. That looks OK. End-of-quarter DSO decreased 8.7% from the prior-year quarter. It was down 4.9% versus the prior quarter.
DanielNenni SemiWiki.com
Are You Watching This Trend at #TSMC? fool.com/investing/gene…

Margins matter. The more Taiwan Semiconductor Manufacturing (NYSE: TSM ) keeps of each buck it earns in revenue, the more money it has to invest in growth, fund new strategic plans, or (gasp!) distribute to shareholders. Healthy margins often separate pretenders from the best stocks in the market. That’s why we check up on margins at least once a quarter in this series. I’m looking for the absolute numbers, comparisons to sector peers and competitors, and any trend that may tell me how strong Taiwan Semiconductor Manufacturing’s competitive position could be.

Here’s the margin picture for Taiwan Semiconductor Manufacturing over the past few years:

Here’s how the stats break down:

  • Over the past five years, gross margin peaked at 49.4% and averaged 45.8%. Operating margin peaked at 40.1% and averaged 35%. Net margin peaked at 40% and averaged 34.5%.
  • TTM gross margin is 48.7%, 290 basis points better than the five-year average. TTM operating margin is 36.9%, 190 basis points better than the five-year average. TTM net margin is 36.5%, 200 basis points better than the five-year average.

With recent TTM operating margins exceeding historical averages, Taiwan Semiconductor Manufacturing looks like it is doing fine.

My expert guess is that the semiconductor industry will continue to struggle as a result of the economic uncertainty around the world. Unemployment, debt, housing crisis, over population (7 Billion+ people!); consumers will spend less money on electronics next year. To make things worse, semiconductor inventories are at pre-recession levels. In Q2 2011, the DOI (days of inventory) reached 83.4 days, exceeding the last record high of 83.1 days seen in the first quarter of 2008. The good news is that smart phones are no longer considered a luxury, smart phones are now life lines which means they will continue to hyper drive the semiconductor industry for years to come. China is hugely subsidizing mobile phones and India launched a $35 tablet ($60 cost) so the internet will be coming before indoor plumbing in some regions.

In regards to TSMC, it is all good news. Take a look at the charts and you will see an extremely healthy company in a VERY competitive market and the MOST economically challenging times the semiconductor industry has ever seen. TSMC has already won the 28nm node and 20nm is not far behind. TSMC is easily a $20 stock, believe it.

UMC botched 40nm and is struggling with 28nm, this really breaks my heart as I absolutely respect the UMC engineers. SMIC was a huge disappointment. Backed by the Chinese government and the largest domestic market for consumer electronics, how could they fail? But fail they did. Hopefully the recent re-org will get SMIC back in the foundry game! I also had high hopes for GlobalFoundries as a competitive threat for TSMC. GFI is actually doing quite well, unfortunately we all got carried away in the excitement and unachievable expectations were set. Intel 22nm may be the only real threat to TSMC at 28nm and it will certainly be exciting to see how that all plays out.

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Samsung versus Apple and TSMC!

Samsung versus Apple and TSMC!
by Daniel Nenni on 09-28-2011 at 6:56 am
Categories: Foundries, Intel Foundry, TSMC

Apple will purchase close to eightBILLION dollars in parts from Samsung for the iSeries of products this year alone, making Apple Samsung’s largest customer. Samsung is also Apple’s largest competitor and TSMC’s most viable competitive foundry threat so it was no surprise to see Apple and TSMC team up on the next generations of iProducts. The legal battle between Samsung and Apple did come as a surprise however and will change how we do business for years to come.

“Our mission is to be the trusted technology and capacity provider of the global IC industry for years to come.” TSMC Website

During the past 25+ years I have been to South Korea a dozen or so times working with EDA and SemIP companies in pursuit of Samsung business. South Korea is a great place to visit but South Korea is not a great place to do business (my opinion) due to serious ethical dilemmas. Let’s not forget the Samsung corruption scandalthat engulfed the government of South Korea. Let’s not forget the never ending chip dumping probes. The book “Think Samsung” by ex-Samsung legal counsel accuses Samsung of being the most corrupt company in Asia. So does it really surprise you that Apple is divorcing Samsung for cloning the iPad and iPhone?

I was never an Apple fanboy, always choosing “open” products for my personal and professional needs. If the IBM PC was “closed” and obsessively controlled like Macs, where would personal computing be today? The iPod was the first Apple product to invade my home and only after a handful of other MPEG players failed on me. Without iPod/iTunes where would the music industry be today?

iPad2s came to my house next. Would there even be a tablet market without the iPad? I looked at other tablets but since they were to be gifts to SemiWiki users I had a much more critical eye for quality. I even kept one of the SemiWiki iPad2s which I now use daily. We still have some iPad2s left so register for SemiWiki today and maybe you will win one!

A MacBook Air ALMOST came next, but I chickened out and bought a Dell XPS instead. The support burden of moving my family of six from Dell/HP/Sony laptops to Apple Town was just too much to fathom.

iPhone5s for the entire family will be next, Santa is bringing them for Christmas. I’m tired of my Blackberry and I being out smartphoned by snot nosed iPhone kids. I did look at the Samsung iPhone and iPad clones, and while they are less expensive, my professional experience with Samsung will not allow me to buy their products. I will wait for an Apple flat screen TV as well.

Paul McLellan did a nice write up of “The battle of the Patents” for the wireless business: Apple, Samsung, Microsoft, Oracle, Google, Nokia, and here comes a real threat to the mobile industry, Amazon (Kindle Fire Tablet)!

The Apple / Samsung legal debacle will most definitely change the semiconductor foundry business. Can Samsung or even Intel become “the trusted technology and capacity provider of the global IC industry for years to come”? Not a chance.

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TSMC and Dr. Morris Chang!

TSMC and Dr. Morris Chang!
by Daniel Nenni on 09-05-2011 at 6:14 pm
Categories: Foundries, TSMC

While I was in Taiwan last month battling a Super Typhoon, Morris Chang was in Silicon Valley picking up his IEEE Medal of Honor. Gordon Moore, Andrew Grove, and Robert Noyce all have medals. The other winners, including 10 Nobel prize recipients, are listed HERE. An updated wiki on Dr. Morris Chang is located HERE.

The 12+ hour plane ride home gives a person plenty of time for reflection on why TSMC is so successful. Leadership is certainly important, just take a look at the executive staff on the new TSMC corporate website ( www.tsmc.com ). But in my opinion, TSMC’s success boils down to one thing, they are a dedicated IC foundry that is dependent on its customers and ecosystem partners and TSMC has never forgotten that.

Foundry 2010 Revenues:
(1) TSMC $13B
(2) UMC $4B
(3) GFI $3.5B
(4) SMIC $1.5B
(5) Dongbu $512M
(6) Tower/Jazz $509M
(7) Vanguard $508M
(8) IBM $430M
(9) Samsung $420M
(10) MagnaChip $405M

But if you ask how TSMC and Dr. Morris Chang himself got where they are today it can be summed up in three words: Business Model Innovation. Other business model innovators include: eSilicon, ARM, Apple, Dell, Starbucks, Ebay, Google, etc…. I would argue that without TSMC some of these businesses would not even exist.

Morris Chang’s education started at Harvard but quickly moved to MIT as his interest in technology began to drive his future. From MIT mechanical engineering graduate school Morris went directly into the semiconductor industry at the process level and was quickly moved to management. After completing an electrical engineering PhD program at Stanford, Morris leveraged his process level semiconductor management success and went to Taiwan to head the Industrial Technology Research Institute (ITRI) which lead to the founding of TSMC.

In 1987 TSMC started 2 process nodes behind current semiconductor manufacturers (IDMs). Morris Chang made the first TSMC sales calls with a single brochure: TSMC Core Values: Integrity, commitment, innovation, partnership. 4-5 years later TSMC was only behind 1 node and the orders started pouring in. In 10 years TSMC caught up with IDMs (not Intel) and the fabless semiconductor industry blossomed enabling a whole new era of semiconductor design and manufacturing.

Morris Chang Awards

  • 1998, “Top 25 Managers of the Year” and “Stars of Asia” by Business Week.
  • 1998, “One of The Most Significant Contributors in the 50 years of Semiconductor Industry” by BancAmerica Robertson Stephens.
  • 2000, “IEEE RobertN. Noyce Award” for Exceptional Contributions to Microelectronics Industry.
  • 2000, “Exemplary Leadership Award” from the Fabless Semiconductor Association (GSA).
  • 2005, “Top 10 Most Influential Leaders of the World” by Electronic Business.
  • 2008, “Semiconductor Industry Association’s Robert N. Noyce Award”
  • 2009, “EE Times Annual Creativity in Electronics Lifetime Achievement Award”
  • 2011, IEEE Medal of Honor

Dr. Morris Chang turned 80 on July 10[SUP]th[/SUP] 2011, I have seen him in Fab 12 but we have not met. Morris returned to the CEO job in June of 2009 and is still running TSMC full time as CEO and Chairman. He works from 8:30am to 6:30pm like most TSMC employees and says that a successful company life cycle is: rapid expansion, a period of consolidation, and maturity. The same could be said about Morris himself.

Here is a new 5 minute video from TSMC. I highly recommend watching it:

Pioneer of Dedicated IC Foundry Business Model

Related Blogs:TSMC 28nm / 20nm Update!

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Semiconductor Yield @ 28nm HKMG!

Semiconductor Yield @ 28nm HKMG!
by Daniel Nenni on 08-28-2011 at 4:00 pm
Categories: EDA, Foundries, Solido, TSMC

Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) verification technologies. It has been a bumpy two years certainly, but the results make for a good blog so I expect this one will be well read.

GLOBALFOUNDRIES Selects Solido Variation Designer for High-SigmaMonte Carlo
and PVT Design in its AMS Reference Flow

“We are pleased to work with Solido to include variation analysis and design methodology in our AMS Reference Flow,” said Richard Trihy, director of design enablement, at GLOBALFOUNDRIES. “SolidoVariation Designer together with GLOBALFOUNDRIES models makes it possible to perform high-sigma design for high-yield applications.”

Solido HSMC is a fast, accurate, scalable, and verifiable technology that can be used both to improve feedback within the design loop, as well as for comprehensive verification of yield critical high-sigma designs.

Since billions of standard Monte Carlo (MC) simulations would be required for six sigma verification, most yield sensitive semiconductor designers use a small number of MC runs and extrapolate the results. Others manually construct analytical models relating process variation to performance and yield. Unfortunately, both approaches are time consuming and untrustworthy at 28nm HKMG.

Here are some of the results I have seen during recent evaluations and production use of Solido HSMC:

Speed:

  • 4,700,000x faster than Monte Carlo for 6-sigma analysis
  • 16,666,667x fewer simulations than Monte Carlo for 6-sigma analysis
  • Completed in approximately 1 day, well within production timelines

Accuracy:

  • Properly determined performance at 6-sigma, with an error probability of less than 1e-12
  • Used actual Monte Carlo samples to calculate results
  • Provided high-sigma corners to use for design debug

Scalable:

  • Scaled to 6-sigma (5 billion Monte Carlo samples)
  • Scaled to more than 50 process variables

Verifiable:

  • Error probability was reported by the tool
  • Results used actual Monte Carlo samples – not based on mathematical estimates


Mohamed Abu-Rahma of Qualcomm did a presentation at #48DAC last June in San Diego. A video of his presentation can be seen HERE. Mohamed used Solido HSMC and Synopsys HSPICE for six sigma memory design verification.

Other approaches to six-sigma simulation include:

  • Quasi Monte Carlo (QMC)
  • Direct Model-based
  • Worst-Case Distance (WCD)
  • Rejection Model-Based (Statistical Blockade)
  • Control Variate Model-Based (CV)
  • Markov Chain Monte Carlo (MCMC)
  • Importance Sampling (IS)

None of which were successful at 28nm due to excessive simulation times and the inability to correlate with silicon. Especially the Worst-Case Distance approach, which is currently being peddled by an EDA vendor who’s name I will not mention. They claim it correlates to silicon but it does not! Not even close! But I digress…..

Being from Virage Logic and working with Solido the last two years, this blog is based on my personal experience. If you have hard data that suggests otherwise let me know and I will post it.

I would love to describe in detail how Solido solved this very difficult problem. Unfortunately I’m under multiple NDA’s with the penalty of death and dismemberment (not necessarily in that order). You can download a Solido white paper on high-sigma Monte Carlo verification HERE. There is another Solido white paper that goes into greater detail of how they solved this problem but it requires an NDA. You can also get a Webex HSMC briefing by contacting Solido directly HERE. I observed one just last week and it was quite good, I highly recommend it!

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TSMC 28nm and 20nm Update!

TSMC 28nm and 20nm Update!
by Daniel Nenni on 08-15-2011 at 3:00 pm
Categories: Foundries, TSMC

First, I would like to congratulate Samsung on their first 20nm test chip press release. Some will say it is a foundry rookie mistake since real foundries do not discuss test chip information openly. I like it because it tells us that Samsung is 6-9 months BEHIND the number one foundry in the world on the 20nm (gate-last HKMG) process node. Samsung gave up on gate-first HKMG? 😉

Unfortunately, the latest news out of TSMC corporate is that 28nm revenues will be 1% of total revenues in 2011 versus the forecasted 2%. Xbit Labs did a nice article here. The official word is that:

“The delay of the 28nm ramp up is not due to a quality issue, we have very good tape-outs. The delay of ramp up is mainly because of softening economy for our customers. So, customers delayed the tape-outs. The 28nm revenue contribution in the Q4 2011 will be roughly about 1% of total wafer revenue,” said Lora Ho, senior vice president and chief financial officer or TSMC.

TSMC’s competitors on the other hand, are whispering that there is a 28nm yield problem, using the past 40nm yield ramping issues as a reference point. Rather than speculate and pull things out of my arse I asked people who actually have 28nm silicon how it is going. Unanimously it was, “TSMC 28nm yield is very good!” Altera and Xilinx are already shipping 28nm parts . The other markets I know with TSMC 28nm silicon are microprocessors, GPUs, and MCUs.

“We are far better prepared for 28nm than we were for 40nm. Because we took it so much more seriously. We were successful on so many different nodes for so long that we all collectively, as an industry, forgot how hard it is. So, one of the things that we did this time around was to set up an entire organization that is dedicated to advanced nodes. We have had many, many tests chips run on 28nm, we have working silicon,” said Jen-Hsun Huang, chief executive officer of Nvidia.

It is easy to blame the economy for reduced forecasts after what we went through in 2009 and the current debt problems being over reported around the world. The recent US debt debacle is an embarrassment to every citizen of the United States who votes. Next election I will not vote for ANY politician currently in office, but I digress….

So the question is: Why do you think TSMC is REALLY reporting lower 28nm revenues for 2011?

Consider this: TSMC is the first source winner for the 28nm process node, without a doubt. All of the top fabless semiconductor companies will use TSMC for 28nm including Apple, AMD, Nvidia, Altera, Xilinx, Qualcom, Boradcom, TI, LSI, Marvell, Mediatek, etc……. These companies represent 80%+ of the SoC silicon shipped in a year (my guess).

One of the lessons semiconductor executives learned at 40nm is that silicon shortages delay new product deliveries, which cause billions of dollars in lost stock valuation, which gets you fired. Bottom line is semiconductor executives will be much more cautious in launching 28nm products until there is excess capacity, which will be mid 2012 at the earliest.

Other relevant 2011 semiconductor business data points:

[LIST=1]

  • The Android tablet market is DOA (iPad2 rules!)
  • The PC market is dying (Smartphone and tablets, Duh)
  • Mobile phones are sitting on the shelf (Are we all waiting for the iPhone5?)
  • Anybody buying a new car this year? Not me.
  • Debt, debt, unemployment, debt, debt, debt…….

    Not all bad news though, last Friday was the 30[SUP]th[/SUP] anniversary of the day I met my wife and here is how great of a husband I am: First I went with my wife to her morning exercise class. 30+ women and myself dancing and shaking whatever we got. It was a very humbling experience, believe me! Next was a picnic on Mt Diablo recreating one of our first dates, then dinner and an open air concert at Blackhawk Plaza. Life as it should be!


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    TSMC Financial Status Plus OIP Update!

    TSMC Financial Status Plus OIP Update!
    by Daniel Nenni on 07-05-2011 at 8:00 am
    Categories: Foundries, GlobalFoundries, TSMC

    Interesting notes from my most recent Taiwan trip: Taiwan unemployment is at a record low. Scooters once again fill the streets of Hsinchu! TSMC will be passing out record bonuses to a record amount of people. TSMC Fab expansions are ahead of schedule. The new Fab 15 in Taichung went up amazingly fast with equipment moving in later this year. When was the last time you saw a fab built ahead of schedule and under budget? Simply amazing! Taiwan is also ready to overtake Japan as the world’s largest semiconductor materials market. The Taiwan market grew from $6.9 billion in 2009 to estimated $9.1 billion in 2010, showing 36%+ growth. Go Taiwan!

    The Motley Fool did a nice TSMC financial article with pretty pictures. I like pretty pictures. The bottom line is that not only is TSMC the largest semiconductor foundry, TSMC is also the most profitable. The important point here is margins. Margins translates into pricing flexibility as supply outpaces demand, which is coming, believe it! Semiconductor manufacturing capacity utilization today is running at 90%+ in most segments. With all the new fab space coming online from TSMC, Samsung, Intel, and GlobalFoundries in 2012 it may be a different story. Either way TSMC wins.

    Unfortunately Motley Fool does not know semiconductors as they listed NVIDIA and LDK Solar as industry peers/competitors! DOH! One of the most amusing things I do for money is consult with Wall Street types and explain exactly what the semiconductor market is and who the real players are. I also slip in some EDA and Semi IP information whenever possible. Even with the recent acquisitions, Wall Street simply does not care about EDA, but I digress.

    The one semi-relevant example Motley Fool uses is number four foundry, SMIC. TSMC Gross Margins are 49.6% versus SMIC at 20.8%. UMC, the number two foundry, is at 27.5%. GlobalFoundries financials are private but I will see what I can find out. Intel and Samsung will never tell foundry capacity or margin numbers so I shouldn’t even be mentioning them in the same paragraph as the real foundries.

    Coming this fall from TSMC is the new and improved Open Innovation Platform Ecosystem Forum. TSMC is preparing a massive design ecosystem event on Tuesday, October 18th at the San Jose Convention Center. A call for papers already went out, 18 papers will be presented to an open forum of industry executives from TSMC, ecosystem partners, and customers. This is a DO NOT MISS event! There will be focused breakout sessions on all manner of design issues AND a pavilion with around 80 TSMC Design Ecosystem partners showing their wares. Plus, I will be there (free food), such a deal. The food is always good at TSMC events!

    The Open Innovation Platform® is the substantiation of TSMC’s Open Innovation model that brings together the thinking of customers and partners under the common goal of shortening design time, minimizing time-to-volume and speeding time-to-market, and ultimately time-to-money.

    No doubt this event will be sold out. Follow SemiWiki.com for TSMC OIP updates coming soon.

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    TSMC Versus Intel: The Race to Semiconductors in 3D!

    TSMC Versus Intel: The Race to Semiconductors in 3D!
    by Daniel Nenni on 06-26-2011 at 4:00 pm
    Categories: Foundries, TSMC

    While Intel is doing victory laps in the race to a 3D transistor (FinFet) @ 22nm, TSMC is in production with 3D IC technology. A 3D IC is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The question is which 3D race is more important to the semiconductor industry today?

    Steve Liebson did a very nice job in his blogs: Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part I) and (Part II). DR. Chenming Hu is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was he was the Chief Technology Officer of TSMC. Hu coined the term FinFET 10+ years ago when he and his team built the first FinFETs and described them in a 1999 IEDM paper. The name FinFET because the transistors (technically known as Field Effect Transistors) look like fins. Hu didn’t register patents on the design or manufacturing process to make it as widely available as possible and was confident the industry would adopt it. Well, it looks like he was right!

    In May of this yearIntel announced Tri-Gate (FinFET) 3D transistor technology at 22nm for the Ivy Bridge processor citing significant speed gains over traditional planar transistor technology. Intel also claims the Tri-Gate transistors are so impressively efficient at low voltages they will make the Atom processor much more competitive against ARM in the low power mobile internet market. Intel has a nice “History of the Transistor” backgrounder HERE in case you are interested.

    Time will tell but I think this could be another one of Intel’s billion dollar mistakes. A “significant” speed-up for Ivy Bridge I will give them, but a low power competitive Atom? I don’t think so. TSMC’s 3D IC technology on the other hand is said to achieve performance gains of about 30% while consuming 50% less power. Intel already owns the traditional PC market so trading the speed-up of 3D transistor technology for lower power planar transistors is a mistake. A mistake that will allow ARM to continue to dominate the lucrative smartphone and tablet market.

    Intel also does not mention 22nm Tri-Gate manufacturing costs which is key if they are serious about the foundry business. I still say they are not serious and this is another supporting data point. Foundry capacity will soon outpace demand so low manufacturing costs will be a critical competitive advantage.

    TSMC has chosen to wait until 14nm to bring 3D transistor technology to the foundry business. Given that TSMC is the undisputed foundry champion and the father of the FinFet is a “TSMC Distinguished Professor of Microelectronics at University of California”, my money is again on TSMC. I won my previous bet of Gate-last HKMG (TSMC) versus Gate-first (IBM/Samsung) so I’m letting it ride on 14nm being the correct node for FinFets.

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