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Did Apple Influence AMD’s TSMC Foundry Switch?

Did Apple Influence AMD’s TSMC Foundry Switch?
by Ed McKernan on 11-27-2011 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC

During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3 due in 2012 highlight the extent to Apple’s involvement in design and investment to guarantee supply at a much reduced cost so that competitors are left gasping. Turning to the processor world, we know Apple has selected TSMC to Fab their 28nm A6 processor. Why not pull AMD into the Apple-TSMC supply chain ecosystem in order to outmaneuver the raft of Intel based Ultrabook PCs that are headed to the market in 2012?

Continue reading “Did Apple Influence AMD’s TSMC Foundry Switch?”

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Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am
Categories: EDA, Foundries, Siemens EDA, TSMC

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were extended by Mentor Graphics for the Calibre tool to handle TSV (Thru Silicon Via) technology. This extension is called Calibre 3DSTACK.

With TSV each die now becomes double-sided in terms of metal interconnect. DRC and LVS have to now verify the TSV, plus front and back metal layers.

The new 3DSTACK configuration file controls DRC and LVS across the stacked die:

A second source that I read was at SOC IP where there were more details provided about the configuration file.

This rule file for the 3D stack has a list of dies with their order number, postion of each die, rotation, orientation, location of the GDS layout files and associated rule files and directories.

To do the parasitic extraction requires new information about the size and electrical properties of the microbumps, copper pillars and bonding materials.

One methodology is to first run DRC, LVS and extraction on each die separately, then add the interfaces. The interface between the stacked dies uses a separate GDS, and LVS/DRC checks are run against this GDS.

For connectivity checking between dies text labels are inserted at the interface microbump locations.

With these new 3D extensions then Calibre can run DRC, LVS and extraction on the entire 3D stack. A GUI helps you to visual the 3D rules and results from DRC, LVS and extraction:

TSMC Partner of the Year Award
Based on this extension of Calibre into the 3D realm, TSMC has just announced that Mentor was chosen as the TSMC Partner of the Year. IC designers continue to use the familiar Calibre rule decks with the added 3DSTACK technology.

Summary
Yes, 3D-IC design is a reality today where foundries and EDA companies are working together to provide tools and technology to extend 2D and 2.5D flows for DRC, LVS and extraction.

Further Info

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Synopsys Awarded TSMC’s Interface IP Partner of the Year

Synopsys Awarded TSMC’s Interface IP Partner of the Year
by Eric Esteve on 11-09-2011 at 9:19 am
Categories: Foundries, IP, Synopsys, TSMC

Is it surprising to see that Synopsys has been selected Interface IP partner of the year by TSMC? Not really, as the company is the clear leader on this IP market segment (which includes USB, PCI Express, SATA, DDRn, HDMI, MIPI and others protocols like Ethernet, DisplayPort, Hyper Transport, Infiniband, Serial RapidIO…). But, looking five years back (in 2006), Synopsys was competing with Rambus (no more active on this type of activity), ARM (still present, but not very involved), and a bunch of “defunct” companies like ChipIdea (bought by MIPS in 2007, then sold to Synopsys in 2009), Virage Logic (acquired by Synopsys in 2010)…At that time, the Interface IP market was weighting $205M (according with Gartner) and Synopsys had a decent 25% market share. Since then, the growth has been sustained (see the picture showing the market evolution for USB, PCIe, DDRn, SATA and HDMI) and Synopsys is enjoying in 2010 a market share of… be patient, I will disclose the figure later in this document!

What we can see on the above picture is the negative impact of the Q4 2008-Q1/Q2/Q3 2009 recession on the growth rate for every segment – except DDRn Memory Controller. Even if in 2010, the market has recovered, we should come back to 20-30% like growth rate only in 2011. What will happen in 2012 depends, as always, of the health of the global economy. Assuming no catastrophic event, 2010/2011 growth should continue, and the interface IP market should reach in 2012 a $350M level, or be 58% larger than in 2009 (a 17% CAGR during these 3 years).

The reasons for growth are well known (at least for those who read Semiwiki frequently!): the massive move from parallel I/Os to high speed serial, the ever increasing need for more bandwidth, not only in Networking, but also in PC, PC peripheral, Wireless and Consumer Electronic segments – just because we (the end user) exchange more data through Emails, Social Media, watch movies or listen music on various, and new, electronic systems. Also because these protocols standards are not falling in commoditization (which badly impact the price you sell Interface IP), as the various organizations (SATA, USB, PCIe, DDRn to name the most important) are releasing new protocol version (PCIe gen-3, USB 3.0, SATA 6G, DDR4) which help to keep high selling price for the IP. For the mature protocols, the chip makers expects the IP vendors to port the PHY (physical part, technology dependant) on the latest technology node (40 or 28 nm), which again help to keep price in the high range (half million dollar or so). Thus the market growth will continue, at least for the next three to four years. IPnest has built a forecast dedicated to these Interface IP segments, up to 2015, and we expect to see a sustained growth for a market climbing to a $400M to $450M range (don’t expect IPNEST to release a 3 digit precision forecast, this is simply anti-scientific!)…

But what about Synopsys’ position? Our latest market evaluation (one week old) integrated in the “Interface IP Survey 2005-2010 – Forecast 2011-2015” shows that for 2010, Synopsys has not only kept the leader position, but has consolidated and has passed from a 25% market share in 2006 to a 40%+ share in 2010. Even more impressive, the company is getting at least 50% more market share (sometime more than 80%) in the segments where they are playing, namely USB, PCI Express, SATA, DDRn, with the exception of HDMI, where Silicon Image is really too strong- on a protocol they have invented, that make sense!

All of the above explains why TSMC has made the good choice, and any other decision would not have been rational… except maybe to decide to develop (or at least market) themselves the Interface IP functions, like the FPGA vendors are doing…

By the way, if you plan to attend IP-SoC 2011 in December 7-8[SUP]th[/SUP] in Grenoble, don’t miss the presentation I will give on the Interface IP market, see the Conference agenda.

Eric Esteve from IPNEST – Table of Contentfor “Interface IP Survey 2005-2010 – Forecast 2011-2015” available here

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3D Transistors @ TSMC 20nm!

3D Transistors @ TSMC 20nm!
by Daniel Nenni on 11-06-2011 at 12:51 pm
Categories: Foundries, TSMC

Ever since the TSMC OIP Forum where Dr. Shang-Yi Chiang openly asked customers, “When do you want 3D Transistors (FinFETS)?” I have heard quite a few debates on the topic inside the top fabless semiconductor companies. The bottom line, in my expert opinion, is that TSMC will add FinFETS to the N20 (20nm) process node in parallel with planar transistors and here are the reasons why:



Eliminating EXCESS: In the next few years, traditional planar CMOS field-effect transistors will be replaced by alternate architectures that boost the gate’s control of the channel. The UTB SOI

replaces the bulk silicon channel with a thin layer of silicon mounted on insulator. The FinFET turns the transistor channel on its side and wraps the gate around three sides. (Click to enlarge)

The1999 IDM paper Sub 50-nm FinFET: PMOSstarted the 3D transistor ball rolling then in May of 2011 Intel announceda production version of a 3D transistor (TriGate) technology at 22nm. Intel is the leader in semiconductor process technologies so you can be sure that others will follow. Intel has a nice “History of the Transistor” backgrounder in case you are interested. Probably the most comprehensive article on the subject was just published by IEEE Spectrum “Transistor Wars: Rival architectures face off in a bid to keep Moore’s Law alive”. This is a must read for all of us semiconductor transistor laymen.


DOWN AND UP: A cross section of UTB SOI transistors and a micrograph of an array of FinFET transistors .

Why the push to 3D transistors at 20nm?

Reason #1 is because of scaling. From 40nm to 28nm we saw significant opportunities for a reduction in die size and power requirements plus an increase in performance. The TSMC 28nm gate-last HKMG node will go down in history as the most profitable node ever, believe it! Unfortunately standard planar transistors are not scaling well from 28nm to 20nm, causing a reduction of the power/die savings and performance boost customers have come to expect from a process shrink. From what I have heard it is half what was expected/hoped for. As a result, TSMC will definitely offer 3D transistors at the 20nm node, probably as a mid-life node booster.



Shrinking returns: As transistors got smaller, their power demands grew. By 2001, the power that leaked through a transistor when it was off was fast approaching the amount of power needed to turn the transistor on , a warning sign for the chip industry. As these Intel data show, the leakage problem eventually put a halt to the transistor scaling , a progression called Dennard’s law. Switching to alternate architectures will allow chipmakers to shrink transistors again, boosting transistor density and performance.

Reason #2 is because TSMC can and it will offer a significant competitive advantage against the second source foundries (UMC, GFI, SMIC). DR. Chenming Hu is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was the Chief Technology Officer of TSMC. Hu coined the term FinFET 10+ years ago when he and his team built the first FinFETs and described them in the 1999 IEDM paper. The name FinFET because the transistors (technically known as Field Effect Transistors) look like fins. Hu didn’t register patents on the design or manufacturing process to make it as widely available as possible and was confident the industry would adopt it. Well, he was absolutely right!

The push for 3D transistors clearly shows that the days of planar transistor scaling will soon be behind us. It also shows what lengths we will go through to continue Moore’s Law. Or as TSMC says “More-than Moore Technologies”.

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High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!
by Daniel Nenni on 11-01-2011 at 9:00 am
Categories: EDA, Foundries, Solido, TSMC

Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER MOSFET/Analog Switch/ADC/CDA/PLL sold to companies like Fujitsu, Toshiba …etc.

We used to have a project when I worked on R&D to simulate the process based on the device architecture and send the out data to a simulator called PICE which is a device simulator and the output again was sent to the input of Spice simulator , as the Process simulator , the device simulator and spice simulator are connected.

We can easily define the performance of the targeted analog circuit with variation of process recipe and device structures, we can also predict the yield of each corner with running the spice PVT simulation against the six sigmal spice models. However, as you know, the performance always has to compromise with the reliability, and you can’t run the circuit simulation together with the reliability models, because no such models are available.

As a result I do not pay much attention to the result of spice simulation, because it can never tell you what the reliability will be with the result of spice simulation, and I still believe real corner lot wafer is the best way to verify the performance, yield and reliability.

Hi Edward,

Process variation is of great interest at 28nm and even more at 20nm. In a recent independent survey, variation-aware custom IC design was ranked the number one area requiring advancement over the next two years. The survey revealed:

[LIST=1]

  • 53% of design groups missed deadlines or experienced respins due to variation issues
  • Designers experienced an average 2 month delay due to variation issues
  • Designers spent an average 22% of design time on variation issues

    For further information, see the Gary Smith EDA analyst report on variation design.

    Here is a recent webinar done by Solido and TSMC on High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design.

    Attendees of this webinar learned:

    [LIST=1]

  • Variation challenges in custom IC design
  • Variation-aware solutions available in the TSMC AMS reference flow
  • Methods to develop and verify designs over PVT corners in less time
  • How to efficiently apply Monte Carlo techniques in design sign-off
  • How Monte Carlo is really possible up to 6-sigma
  • Customer case studies of the above methods

    Solido customer case studies include:

    [LIST=1]

  • NVIDIA for memory, standard cell, analog/RF design
  • Qualcomm for memory design
  • Huawei-HiSilicon for analog design
  • Qualcomm for I/O design
  • Anonymous for analog/RF design

    Presenters:

    [LIST=1]

  • Nigel Bleasdale, Director of Product Management, Solido Design Automation
  • Jason Chen, Design Methodology and Service Marketing, TSMC

    Audience: Circuit Designers, Design Managers, CAD Engineers

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    ARM TechCon 2011 Trip Report and Sailing Semiconductors!

    ARM TechCon 2011 Trip Report and Sailing Semiconductors!
    by Daniel Nenni on 10-26-2011 at 9:37 pm
    Categories: Arm, Cadence, IP, Siemens EDA, TSMC

    This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat which is currently in Mexico for the Winter. I’ve sailed on the Esmeralda before but she has just been sold so this was a momentous occasion. Uncle Jim has some health issues so he will be a land locked for the rest of his days. Sailing up and down the Coast is very hard work, believe it!

    On the semiconductor side, sailing has come a long way since Esmeralda was first launched. The marine electronics available today are amazing and the ability to run those low-power semiconductor devices via the wind and sun is simply incredible. There should be an ARM Inside sticker on every sailboat! Even the shower is 100% solar and let me tell you that water gets hot! Esmeralda can also desalinate saltwater faster than we could drink it! As the picture suggests we were 3G enabled so, yes, I sailed the internet! Uncle Jim did his best to keep Esmeralda up to date but now technology moves much faster than he can.

    I chose Tuesday for ARM TechCon to see the keynotes by TSMC’s Dr. Shang-Yi Chiang, my favorite EDA CEO Dr. Wally Rhines, and Cadence Sr VP Dr. Chi-Ping Hsu. Somebody from the conference called me tonight (Wednesday) and asked why I didn’t attend. Well, you gave me a one-day pass that’s why! But seriously, why the strong ARM tactic? The place was jam PACKED with semiconductor professionals. Having 99.99% market share must be nice!

    Shang-Yi’s presentation was similar to the one at OIP last week which I blogged about HERE. According to Shang-Yi, the biggest problems to face the semiconductor industry in the years to come will be more economic than technical, citing the increasing costs of wafers as geometry decreases and density increases. He also stated that FinFets will keep semiconductors scaling through the 14nm and 7nm nodes. I certainly hope he is right. I have 4 kids to put through college.

    Wally’s presentation was again by far the best. I expected a rehashed version of his OIP speech, “Accelerating Innovation Through Collaboration” which I blogged about HERE, but no, he pulled out another excellent presentation, “Creating Measurable Value Through Differentiation”. Every CEO in the semiconductor ecosystem should memorize this one! Why have I not seen any press on this? SemiWiki blogger Dr. Paul McLellanwill did a more thorough blog on it HERE.

    Chi-Ping’s presentation was the biggest disappointment, I actually walked out. I know Chi-Ping from the Avanti days and can tell you that material did not come from him. Cadence marketing people clearly possessed him with infomercials and all! He even mentioned EDA360!?!?!? Richard Goering’s blog on it, “ARM TechCon Address: High Stakes at Low Process Nodes” was much better than the presentation itself.

    ARM did not feed the media but thankfully Jim Lai, President of Global Unichip, invited me to lunch so I did not starve. I will blog about our lunch conversation this weekend but let me tell you this, the semiconductor design ecosystem is about to change once again!

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    TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report

    TSMC 2011 Open Innovation Platform Ecosystem Forum Trip Report
    by Daniel Nenni on 10-23-2011 at 3:00 pm
    Categories: EDA, Foundries, TSMC

    The TSMC OIP conference was Monday and Tuesday of last week. You have probably NOT read about it since it was invitation only and press was not invited. Slides were not made available (except for Mentor), no photos or video were allowed, it was a very private affair. Given that, I won’t be able to go into great detail but I will give you the impression it left on me and I will share slides from the best vendor presentation given on the second day.

    TSMC OIP day 1 was for ecosystem partners (EDA, IP, Design Services) and I would say there were about 200 of us. My badge was courtesy ofSolido Design (I do the foundry work for Solido). Presentations were made by Cliff Hou, Vice President of Design Enablement, and LC Lou, Senior Director of IP Development and a couple of other TSMC guys that I did not know. I have worked with both Cliff and LC over the years and have a great respect and trust for them.

    28nm and 20nm were discussed in great detail in regards to design enablement and IP. It was very clear that TSMC is finished with 28nm which ramped 3 times faster than 40nm. All 28nm process nodes: 28HP, 28HPL, 28LP and 28HPM (M=mobile) are in production with thousands of wafers already shipped to customers. This tracks with what I have heard from TSMC’s top customers, 28nm silicon is out and working. The first 20nm production wafers are scheduled for mid 2012. This also tracks with what customers have told me, who are finishing up 20nm PDKS in time for Christmas.

    The technical deep dive was on RDRs (restricted design rules) which are new in 28nm. TSMC said it took customers about a month to adjust to RDRs which may be a little optimistic. The 28nm DRM (design rule manual) is significantly larger than 40nm, meaning the rules are more difficult to describe. Feedback I got from customers however was that RDRs made their life easier and without RDRs 28nm would not have yielded well at all.

    3D IC was discussed in great detail which is a blog in itself. The takeaway here is that TSMC is leading the way in 3D IC, believe it. The other interesting topic was LDEs (layout dependent effects). New effects are coming at 20nm so you can bet LDE will be a big part of the next round of TSMC reference flows (13.0) you will see at the 2012 Design Automation Conference in San Francisco. These reference flows will probably be at 20nm since DAC is mid 2012, same as TSMC 20nm availability. Early access to process technology by both partners and customers was mentioned throughout the two days and I can tell you TSMC is doing much better with early access than other foundries, which was a clear differentiator for the top fabless companies at 28nm.

    Day 2 was for customers which I would guess was close to a thousand people. Rick Cassidy, President of TSMC North America, did the keynote. Side note: Rick is a West Point graduate which may explain his no nonsense speaking style. Shang-Yi was next then Cliff Hou. The hot topic here was FinFets. I have blogged about this before but the message that day was FinFets would have delayed 20nm so TSMC stuck with planar transistors. The FinFet design ecosystem challenge was discussed (3D extraxtion, modeling, etc…) and TSMC flat out asked customers if they wanted FinFets for 14nm (2015). The customers I talked to will look at the technical versus time-to-market trade-offs of FinFets which is still being calculated.

    Vendor presentations were next from Mike Inglis (ARM), Aart de Geus (Synopsys), Lip-bu Tan (Cadence), and Wally Rhines (Mentor). Mentor was the only vendor “open enough” to send me slides so that is the only presentation I will mention. According to Wally 28/20nm will be a “Golden Era” for foundries. Massive capital investment by foundries will yield (pun intended) very cost effective wafers that will absorb existing products at the higher nodes. 28/20nm cost and capability will also drive new applications and accelerate semiconductor industry growth for years to come. Absolfreakinlutely!

    Wally’s presentation has 45 slides and several important points which should be independent blogs. His last slide is my favorite however, it is his personal collaboration ecosystem. My personal collaboration ecosystem is much larger of course since it includes all of you.

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    Mentor at the TSMC Open Innovation Platform Ecosystem Forum

    Mentor at the TSMC Open Innovation Platform Ecosystem Forum
    by Daniel Payne on 10-17-2011 at 3:14 pm
    Categories: EDA, Foundries, Siemens EDA, TSMC

    EDA companies and foundries must closely collaborate in order to deliver IC tool flows that work without surprises at the 40nm and 28nm nodes.

    Tomorrow in San Jose     you can attend this 4th annual event hosted by TSMC along with Mentor Graphics and other EDA and IP companies.

    Here are some of the topics that will interest IC designers using Mentor tools:

    iLVS: Accessible, Supportable Paradigm for Circuit Verification at Advanced Nodes (2:30PM, EDA Track)
    Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. The number of layers and layer derivations are increasing and the complexity of devices, especially Layout Dependent Effects (LDS), becomes harder and harder to model. In the past, customers could take a foundry rule deck and easily modify it to include their own device models for transistors, resistor, capacitors, inductors, etc., and even augment the deck with their own checks. At 40nm, 28nm, few customers are able to do this confidently. To address this situation, TSMC and Mentor Graphics will discuss how they collaborated to define iLVS, a syntax that provides customers with a more easily adaptable solution to their circuit verification needs. Using iLVS, users can more easily modify and augment foundry rule decks, yet still adhere to the modeling and manufacturing intent captured in these decks.

    Keys to Successful DFM Partnership (4:00PM,IP/EDA/Services Track)
    DFM is now a known necessity for advanced nodes. But a successful DFM strategy is more than a “push button” solution. It depends on a synergistic combination of tool technology and design methodology, and close collaboration with the foundry. In this session, CSR and Mentor will relate their personal experiences with DFM, its implementation in the TSMC ecosystem, discuss critical factors that determine the difference between success and failure in actual practice.

    Challenges and Directions for Next Generation 3D-IC (4:30PM, EDA Track)
    The IC industry is steadily moving to the third dimension of scaling, i.e., stacking die vertically using through silicon vias (TSVs) to make inter-die connections in a manner analogous to copper vias in multi-layer printed circuit boards (PCBs), but on a much smaller scale. The 2.5D interposer solution is here today, but next generation, ergo full 3D, will bring additional complexities. For example, when TSVs are introduced into the active area of an IC, things get complicated due to complex electrical, mechanical stress and thermal interactions that impact circuit performance and reliability. In this session Qualcomm and Mentor Graphics will discuss some of the challenges of designing 3D-ICs and what the ecosystem is doing to provide the needed methods and tools to make next generation 3D-IC a reality.

    Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes (5:00PM,IP/EDA/Services Track)
    Preventing electrical circuit failure is a growing concern for IC designers today. For certain types of failures such as Electrostatic discharge (ESD) issues, there are well established best practices and design rules that circuit designers should be adhering to. Other issues are more recent, such as the best way to design circuits that cross different voltage regions on a chip. While these topics are not unique to a specific technology node, in particular for analog mixed signal they become increasingly critical as the oxides get thinner for the most advanced nodes and as circuit designers continue to put more and more voltage regions on-chip. To validate that circuits have robust protection from electrical failure, TSMC and MGC will present how they have partnered to define and develop rule decks that enable automatic advanced circuit verification to address these issues at the 28nm and 40nm nodes.

    Information on the TSMC Open Innovation Platform Ecosystem Forum is here.

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    TSMC Gets Fooled Again!

    TSMC Gets Fooled Again!
    by Daniel Nenni on 10-16-2011 at 2:51 pm
    Categories: Foundries, TSMC

    If you follow the SemiWiki Twitter feed you may have noticed that The Motley Fool (Seth Jayson) did three more articles on TSMC financials. The first Foolish article was blogged on SemiWiki as “TSMC Financial Status and OIP Update”.

    The next three Fool Hardy articles look at cash flow (the cash moving in and out of a business), accounts receivable (AR), days sales outstanding (DSO) and a closer look at margins. All three articles are interesting reads so if you have the time I would definitely click over. If not, here are the cool pictures and my expert guess of the foundry business going forward.
    Don’t Get Too Worked Up Over #TSMCEarnings http://www.fool.com/investing/general/2011/10/04/dont-get-too-worked-up-over-taiwan-semiconductor-.aspx

    Over the past 12 months, Taiwan Semiconductor Manufacturing generated $687.4 million cash while it booked net income of $5,543.0 million. That means it turned 4.5% of its revenue into FCF (Free Cash Flow). That sounds OK.

    However, FCF is less than net income. Ideally, we’d like to see the opposite. Since a single-company snapshot doesn’t offer much context, it always pays to compare that figure to sector and industry peers and competitors, to see how your business stacks up.

    With questionable cash flows amounting to only -1.1% of operating cash flow, Taiwan Semiconductor Manufacturing’s cash flows look clean. Within the questionable cash flow figure plotted in the TTM period above, changes in taxes payable provided the biggest boost, at 1% of cash flow from operations. Overall, the biggest drag on FCF came from capital expenditures, which consumed 92.2% of cash from operations.

    DanielNenni SemiWiki.com
    #TSMCPasses This Key Test fool.com/investing/gene…

    Sometimes, problems with AR or DSO simply indicate a change in the business (like an acquisition), or lax collections. However, AR that grows more quickly than revenue, or ballooning DSO, can also suggest a desperate company that’s trying to boost sales by giving its customers overly generous payment terms. Alternately, it can indicate that the company sprinted to book a load of sales at the end of the quarter, like used-car dealers on the 29th of the month. (Sometimes, companies do both.)

    Why might an upstanding firm like Taiwan Semiconductor Manufacturing do this? For the same reason any other company might: to make the numbers. Investors don’t like revenue shortfalls, and employees don’t like reporting them to their superiors.

    Is Taiwan Semiconductor Manufacturing sending any potential warning signs? Take a look at the chart above, which plots revenue growth against AR growth, and DSO. Will Taiwan Semiconductor Manufacturing miss its numbers in the next quarter or two? I don’t think so. AR and DSO look healthy. For the last fully reported fiscal quarter, Taiwan Semiconductor Manufacturing’s year-over-year revenue grew 5.3%, and its AR dropped 3.9%. That looks OK. End-of-quarter DSO decreased 8.7% from the prior-year quarter. It was down 4.9% versus the prior quarter.
    DanielNenni SemiWiki.com
    Are You Watching This Trend at #TSMC? fool.com/investing/gene…

    Margins matter. The more Taiwan Semiconductor Manufacturing (NYSE: TSM ) keeps of each buck it earns in revenue, the more money it has to invest in growth, fund new strategic plans, or (gasp!) distribute to shareholders. Healthy margins often separate pretenders from the best stocks in the market. That’s why we check up on margins at least once a quarter in this series. I’m looking for the absolute numbers, comparisons to sector peers and competitors, and any trend that may tell me how strong Taiwan Semiconductor Manufacturing’s competitive position could be.

    Here’s the margin picture for Taiwan Semiconductor Manufacturing over the past few years:

    Here’s how the stats break down:

    • Over the past five years, gross margin peaked at 49.4% and averaged 45.8%. Operating margin peaked at 40.1% and averaged 35%. Net margin peaked at 40% and averaged 34.5%.
    • TTM gross margin is 48.7%, 290 basis points better than the five-year average. TTM operating margin is 36.9%, 190 basis points better than the five-year average. TTM net margin is 36.5%, 200 basis points better than the five-year average.

    With recent TTM operating margins exceeding historical averages, Taiwan Semiconductor Manufacturing looks like it is doing fine.

    My expert guess is that the semiconductor industry will continue to struggle as a result of the economic uncertainty around the world. Unemployment, debt, housing crisis, over population (7 Billion+ people!); consumers will spend less money on electronics next year. To make things worse, semiconductor inventories are at pre-recession levels. In Q2 2011, the DOI (days of inventory) reached 83.4 days, exceeding the last record high of 83.1 days seen in the first quarter of 2008. The good news is that smart phones are no longer considered a luxury, smart phones are now life lines which means they will continue to hyper drive the semiconductor industry for years to come. China is hugely subsidizing mobile phones and India launched a $35 tablet ($60 cost) so the internet will be coming before indoor plumbing in some regions.

    In regards to TSMC, it is all good news. Take a look at the charts and you will see an extremely healthy company in a VERY competitive market and the MOST economically challenging times the semiconductor industry has ever seen. TSMC has already won the 28nm node and 20nm is not far behind. TSMC is easily a $20 stock, believe it.

    UMC botched 40nm and is struggling with 28nm, this really breaks my heart as I absolutely respect the UMC engineers. SMIC was a huge disappointment. Backed by the Chinese government and the largest domestic market for consumer electronics, how could they fail? But fail they did. Hopefully the recent re-org will get SMIC back in the foundry game! I also had high hopes for GlobalFoundries as a competitive threat for TSMC. GFI is actually doing quite well, unfortunately we all got carried away in the excitement and unachievable expectations were set. Intel 22nm may be the only real threat to TSMC at 28nm and it will certainly be exciting to see how that all plays out.

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    Samsung versus Apple and TSMC!

    Samsung versus Apple and TSMC!
    by Daniel Nenni on 09-28-2011 at 6:56 am
    Categories: Foundries, Intel Foundry, TSMC

    Apple will purchase close to eightBILLION dollars in parts from Samsung for the iSeries of products this year alone, making Apple Samsung’s largest customer. Samsung is also Apple’s largest competitor and TSMC’s most viable competitive foundry threat so it was no surprise to see Apple and TSMC team up on the next generations of iProducts. The legal battle between Samsung and Apple did come as a surprise however and will change how we do business for years to come.

    “Our mission is to be the trusted technology and capacity provider of the global IC industry for years to come.” TSMC Website

    During the past 25+ years I have been to South Korea a dozen or so times working with EDA and SemIP companies in pursuit of Samsung business. South Korea is a great place to visit but South Korea is not a great place to do business (my opinion) due to serious ethical dilemmas. Let’s not forget the Samsung corruption scandalthat engulfed the government of South Korea. Let’s not forget the never ending chip dumping probes. The book “Think Samsung” by ex-Samsung legal counsel accuses Samsung of being the most corrupt company in Asia. So does it really surprise you that Apple is divorcing Samsung for cloning the iPad and iPhone?

    I was never an Apple fanboy, always choosing “open” products for my personal and professional needs. If the IBM PC was “closed” and obsessively controlled like Macs, where would personal computing be today? The iPod was the first Apple product to invade my home and only after a handful of other MPEG players failed on me. Without iPod/iTunes where would the music industry be today?

    iPad2s came to my house next. Would there even be a tablet market without the iPad? I looked at other tablets but since they were to be gifts to SemiWiki users I had a much more critical eye for quality. I even kept one of the SemiWiki iPad2s which I now use daily. We still have some iPad2s left so register for SemiWiki today and maybe you will win one!

    A MacBook Air ALMOST came next, but I chickened out and bought a Dell XPS instead. The support burden of moving my family of six from Dell/HP/Sony laptops to Apple Town was just too much to fathom.

    iPhone5s for the entire family will be next, Santa is bringing them for Christmas. I’m tired of my Blackberry and I being out smartphoned by snot nosed iPhone kids. I did look at the Samsung iPhone and iPad clones, and while they are less expensive, my professional experience with Samsung will not allow me to buy their products. I will wait for an Apple flat screen TV as well.

    Paul McLellan did a nice write up of “The battle of the Patents” for the wireless business: Apple, Samsung, Microsoft, Oracle, Google, Nokia, and here comes a real threat to the mobile industry, Amazon (Kindle Fire Tablet)!

    The Apple / Samsung legal debacle will most definitely change the semiconductor foundry business. Can Samsung or even Intel become “the trusted technology and capacity provider of the global IC industry for years to come”? Not a chance.