Atrenta/TSMC Soft-IP Alliance: 10 companies make the grade

Atrenta/TSMC Soft-IP Alliance: 10 companies make the grade
by Paul McLellan on 03-05-2012 at 7:30 am

Last May, Atrenta and TSMC announced the Soft-IP Alliance Program which uses SpyGlass and a subset of its GuideWare reference methodology to implement TSMC’s IP quality assessment program. TSMC requires all soft-IP providers to reach a minimum level of completeness before their IP is listed on TSMC online. Since TSMC is so dominant in the foundry business right now (Global struggling with process, Intel talking the talk but not yet really walking the walk, UMC…whatever happened to them anyway?) getting approved and listed with TSMC is extremely important.

Atrenta put everything needed to meet TSMC’s requirements in an IP Handoff Kit. Under the hood this uses SpyGlass’s RTL analysis suite to check for syntax and semantic correctness, simulation-synthesis mismatches, connectivity rules, clock domain crossings, test coverage, timing constraints and…lots more.

Suk Lee of TSMC (my successor at running IC marketing when we were both at Cadence) sees this as measurably improving IP quality. Of course TSMC isn’t directly responsible for IP quality but if IP fails and chips don’t go into production TSMC don’t make any money. Anyway, ten companies have now jumped through all the hoops and qualified their IP for inclusion in the TSMC 9000 IP library.

The companies in this initial program are a veritable who’s who of the IP world (with the notable exceptions of ARM and Synopsys). In alphabetical order so as not to offend anyone:

  • Arteris (NoC)
  • CEVA (DSP cores)
  • Chips&Media (video IP)
  • Digital Media Professionals (graphics IP)
  • Imagination Technologies (GPU cores)
  • Intrinsic-ID (security IP)
  • MIPS Technologies (CPU cores)
  • Sonics (NoC)
  • Tensilica (reconfigurable processors and cores)
  • Vivante (GPU cores)

Now that the dominant way to build an SoC is through assembling IP, the issue of IP quality is is a huge problem and a mixture of tools, methodologies, standards and certification is for sure the way to address it.


TSMC 28nm Yield Explained!

TSMC 28nm Yield Explained!
by Daniel Nenni on 03-04-2012 at 4:00 pm


Yield, no topic is more important to the semiconductor ecosystem. After spending a significant part of my career on Design for Manufacturability (DFM) and Design for Yield (DFY), I’m seriously offended when semiconductor professionals make false and misleading statements that negatively affects the industry that supports us.
Continue reading “TSMC 28nm Yield Explained!”


The Qualcomm PUT and The FABulous Year Ahead

The Qualcomm PUT and The FABulous Year Ahead
by Ed McKernan on 01-19-2012 at 5:14 pm

Humor can arise in surprising ways and yet still be disguised to many. As I was researching Qualcomm the other day, I came upon the transcript of their last quarterly earnings and I had to laugh. In the midst of last summer’s European crises, when the Club Med (Greece, Italy, Spain and Portugal) Sovereign Debt was trying to be rolled over with few takers and stocks swooned across the globe, there was Qualcomm injecting a little humor into the markets. You see, in the midst of everyone selling, did a very bullish thing: they sold over $500M of PUTS and collected $75M doing so. At the last earnings call, none of the analysts inquired. Why does a company with $21B in the bank sell PUTS to earn $75M? The answer, I believe has to do with Qualcomm looking to raise its profile even further as they separate themselves from the rest of the mobile ARM camp. However, 2012 will require an even bigger bet the company move.

Throughout the 1990s, Alan Greenspan, disciple of Ayn Rand, and perhaps the most knowledgeable person on the planet in terms of the gives and takes of the economy liked to befuddle congress with presentations that were incomprehensible with the result being that he had great degrees of freedom in pursuing a monetary policy that he believed generated optimum economic growth with low inflation and a stock market that for the most part headed north. An economy, though is a complex thing and even though he thought he could calibrate the health and dynamism by monitoring things like weekly cardboard box production, outside forces could take the stock market down (e.g. the Asian Crises in 1997 and LTCM in 1998). When a crises occurred he would swing into action by implementing what became known as “The Greenspan PUT”. The Fed would immediately lower interest rates and stocks would head higher to the cheers of the investment class. The PUT has limitations, as is seen in our current crises, when debt loads get too large.

Qualcomm’s PUT, in the midst of the European crises was a signal to Wall St. that they believe very good times lie ahead regardless of whether Italy, Greece, France or the whole EU goes in the tank. Although market indications lately show that Europeans will forsake everything to get their hands on an Apple iPAD and iPhone. Perhaps even Italian three hour lunches. Not to worry the money printing has already begun. So, Qualcomm’s selling of PUTS in Q3 was a bullish signal that at the time of expiration in 2H 2012, the stock will be higher than the strike price (I am guessing between $45 and $50 as Qualcomm’s stock flirted with a low of $46). Qualcomm said the breakeven price of the PUT option is roughly $43 a share. Below that they have to write a check to buy the stock back.

Qualcomm’s $21B stash of cash is greater than Intel’s and will soon be three times that of nVidia, Broadcom and Marvell combined who make up the ARM camp that not only are Qualcomm’s chief competitors but licensees. Qualcomm stands as a tall Redwood in a forest of seedlings as it is more than an order of magnitude larger in sales than any of the current ARM campers. But there are major business decisions coming down the pike.

Qualcomm, along with Intel and Apple have the most direct impact on the shaping of the smartphone, tablet, ultrabook mobile Tsunami marketplace and yet each impact it differently. Intel is driving ultrabook to be the form factor that separates them from nVidia and AMD giving them a de-facto Monopoly position in the PC space while also pursuing Apple for the iPhone and iPAD processor business. Apple, we know owns the iTunes Walled Garden Ecosystem that gives them the upper hand in selecting from a cornucopia of suppliers for its next products. You can say that Qualcomm is the winner no matter what communications solution is chosen – whether it is its own chipset or a royalty bearing solution from Broadcom, Intel, Marvell and others. However the big money is in supplying the chips and that can be a problem or opportunity.

As mentioned in previous blogs, the economics of Mobile Tsunami are different than the PC market. Apple and Samsung continue to go Vertical in their supply chain to remove excessive margins. In return for a capital investment and guaranteed demand, Apple gets vendors to drop ASPs and margins. Intel is approaching Apple with a production model that can retain its standard 50-60% Gross Margins but ASPs lower than Samsung due to their 2-3 year process lead. Qualcomm on the other hand sells chips that include the TSMC margin on top of their own 60%+ gross margin.

Bottom line: Does Qualcomm use its $21B cash to build a fab to eliminate TSMC margins and build next generation communications chips that aren’t available elsewhere? Do they approach Intel to Fab next generation standalone chips while offering Intel first rights on “volume integrated communications.” I don’t see Qualcomm moving to a complete IP model. However, the maturation of the very high volume mobile market combined with the economics suggest that the winners will either own Fabs or be IP Houses and a shakeout will take place among the Fabless. There is room for one profit margin, not two – unless you build at Intel. 2012 could be a very decisive year for Qualcomm.

FULL DISCLOSURE: I am Long AAPL, INTC, ALTR, QCOM.


Tracking the Big Semiconductor Story of 2012

Tracking the Big Semiconductor Story of 2012
by Ed McKernan on 01-06-2012 at 3:56 pm

It’s just a matter of time – perhaps just a few months – before the greatest mystery of the semiconductor industry is revealed and the peaceful co-existence of the Fab vs Fabless world is blown apart. An arms race was started by Intel to challenge TSMC and Samsung on who would control not only the high valued processor but soon to be much higher valued NAND Flash and SRAM that define mobility and data center peak performance efficiency. It is not, as many may claim, a battle between x86 and ARM architectures, it is rather an SRAM – NAND dominant memory based platform battle. The shift in our understanding will help explain the mystery as to why Intel is doubling Fab capacity starting in 2012 with the 22nm process even though the PC and server markets are expected to grow in low double digits.

I have written previously about the $10.8B capex build that Intel just completed in 2011. During these past 12 months at every earning call or analyst conference, Intel executives have been cross checked on the wisdom of the massive build out and whether there would be delays, slowdowns, cancellations, pushouts etc… Otellini and company stuck to the strategy and to add a little gasoline to the fire decided to bedevil the analysts with dividend hikes and massive stock buybacks, which will accelerate earnings in 2012 and beyond. This is like FDR telling the war department to get cranking on 50 more aircraft carriers in 1944-45 after having built 83 in the two years prior even though the remaining Japanese carriers numbered in the single digits and the Germans had none to begin with.

It finally occurred to me over the holidays as I was reading the estimates of the Ivy Bridge die size at roughly 25% smaller than the 32nm Sandy Bridge die that Intel had much bigger plans in store for 2012. Ivy Bridge is a shrink of Sandy Bridge with a beefed up graphics controller in order to support DirectX 11 but unlike previous shrinks – there are no additional processor cores. And yet Intel has rushed the conversion of three fabs to 22nm, added a 4[SUP]th[/SUP] fab for 22nm, broke ground on a 14nm development fab that is 60% larger than the previous in order to ramp production immediately and then to top it off decided to build a new 14nm production Fab for late 2013 production ramp. According to Intel, total fab square footage by end of 2013 will be twice what it is today. There are three possible markets, beyond what Intel is building for today that will take advantage of this capacity – and I believe all three will see the light of day in 2012.

The first and obvious one is that Apple will be moving into Intel’s Fabs starting sometime in 2012. Apple’s incredible growth planned for 2012 based on roughly 300M CPUs (Closing in on the number of x86 chips Intel ships) can only be stopped by the words “Lines Down.” The Japanese earthquake and Thailand Floods have exposed the fallacy of the taut just-in-time manufacturing philosophy. No amount of build-ahead stocking can be as effective or economical to Apple as having multiple Fabs building the same product worldwide with guarantees of upside to replace any loss due to “Acts of God” or the imposition of trade barriers that are in the thoughts of many politicians. Furthermore, one can not overlook the trashing of the US dollar that has taken place during the Bush-Obama years that works to the favor of companies who have production facilities in the US (thus Samsung’s new Fab in Texas). Ensconced in Taiwan, TSMC’s business model is at risk to being uncompetitive if the dollar continues to decline. Intel, on the other hand is way ahead of the curve with Fabs in Oregon, Arizona, New Mexico, Ireland and Israel. And when all the dust settles, will probably pickup a certain fab in Dresden at fire sale prices in order to setup a very public cross Atlantic Ocean auction to decide who will be home for the world’s first 450mm wafer. Unless America has a Sputnik Moment, my bet is on the region with the better Bureaucrats.

Tim Cook’s master logicians have implemented the world’s first Virtual Vertical Manufacturing Operation with relatively little money down but first dibs on the latest technologies at Costco prices. They will not have the same leverage with Intel but they will gain access to the process technology that Qualcomm, nVidia, Broadcom and the rest will not have. So Intel can still make 60% Gross Margins while Apple undercuts their rivals in die size, packaging size, power and cost. 22nm is the process that is sending fears through the fabless community (as Morris Chang recently noted) as Intel has reduced standby power by 10X, meaning ARM’s mobile advantage is gone. Though they operate on different game plans, Intel and Apple have a common goal of knocking Samsung out of the game in order to dominate their respective markets and so they will become Allies in this endeavor. Longer term, Apple will need Intel’s process technology in order to smother Amazon’s tablet effort before it gains steam.

Micron’s latest earnings conference call can be described in short as toss the DRAM overboard, it’s Game-On in the battle for NAND Flash Supremacy. The Intel-Micron joint venture looks to leverage Intel’s process lead with Micron’s low overhead business model to win the battle for not only SSDs but also in the die stacked x86CPU+Chipset+NAND configuration that will see uplift in the ultrabook market in 2013. Intel will drive ultrabooks in ever smaller, thinner formfactors while raising their semiconductor content to the exclusion of AMD and nVIdia. If Samsung wants a piece of the action, then they may need to acquire AMD and head down the same road. The market dynamics here offer tremendous upside to Intel and will be the 2[SUP]nd[/SUP] area of Fab capacity utilization.

The third market segment that Intel will attack with its new fab capacity is one that is so logical that I can’t believe it is not being discussed more in the semiconductor techno-sphere. And yet to understand it you have to make a connection to the business opportunity that has been discussed in bits and pieces by Otellini and Data Center VP Kirk Skaugen. Back in the first half of 2012, Skaugen mentioned that Intel’s highest end Xeon processor that sells for over $4000 offered the best ROI to data center customers. The payback they saw in using high end Xeons was in months not years. Furthermore, Intel has raised prices on Xeon and not seen push back, meaning prices will continue to march higher. The ROI is driven by the large Level 3 (L3) caches that allow workloads to stay on chip instead of going to DRAM. So the logical conclusion is that Intel should build even bigger caches and charge more money. However the current Xeons are maxed out on die size.

This is where I see Intel building L4 caches stacked with the Xeon die and offering a new level of performance/watt that can be priced hundreds to thousands of dollars more than the current Xeons. What’s more this new business opportunity allows Intel to ramp 14nm sooner (as they have stated is their goal) with an SRAM product that serves as the process pipe cleaner and is a natural as a much faster yield ramp than any processor Intel builds. The new L4 Cache can eat up lots of wafers, effectively that generate 80-90% gross margins and become a new multi-billion $ business.

In just two short years, as 14nm begins to ramp, Intel will be completely transformed as a company. The x86 vs ARM battle will not be fought as the analysts expect. Dominance in the semiconductor business will have been fought over the superiority of the closely coupled CPU – SRAM – NAND platform of which the latter two will play a greater roll in the value of a platform and end up consuming the most die area and wafers in the Fab. The CPU instruction set and architecture are small potatoes in the overall platform.

Of the three contenders, Intel is the best positioned with process technology and current market standing to move mobiles and servers over to the new memory dominating platforms. Samsung is fighting a two front war with Apple and Intel. TSMC is behind in process technology and SRAM design and does not have a play in NAND – perhaps we will see a partnership form with a leading NAND player.

And so now we can sit back and watch how the biggest semiconductor story of 2012 unfolds as Intel launches its 22nm process.

FULL DISCLOSURE: I am Long AAPL, INTC, ALTR, QCOM


GlobalFoundries Versus Samsung!

GlobalFoundries Versus Samsung!
by Daniel Nenni on 11-27-2011 at 7:00 pm

Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!

“With this new collaboration, we are making one of the industry’s strongest manufacturing partnerships even stronger, while giving customers another platform to drive innovation in mobile technology. Customers using this new offering will gain accelerated time to volume production and assurance of supply, and they will be able to leverage significant learning from the foundry industry’s first high-volume ramp of HKMG technology at 32nm in H1 2011,” said Jim Kupec, senior vice president of worldwide sales and marketing at Globalfoundries.

Unfortunately Jim Kupec no longer works for GlobalFoundries and Samsung may be one of the reasons why. In 2010 Globalfoundries and Samsung Electronics said they would synchronize global semiconductor fabrication facilities to produce chips based on a gate-first implementation of 28nm HKMG technology. They will do the same at 20nm switching to Gate-last HKMG. As a result, Globalfoundries and Samsung will be able to make 28nm and 20nm chips for the SAME customers?!?!?!? Putting aside the gritty technical details, what this means is that GFI will have to compete not only with superpower TSMC, but also their PARTNER Samsung. Samsung is not only the second largest semiconductor company, Samsung is also one of the most fiercely competitive companies in the world. Is that really a good idea?

As it turns out it was a very bad idea for a number of reasons. First and foremost is yield. Samsung is the only “Fab Syncing” partner yielding at 28nm Gate-First HKMG (IBM and GFI are not). Remember Samsung is the largest memory maker so they know how to ramp yield quickly at any node. Are they sharing that manufacturing expertise with GFI and other Common Platform members? Not now, not ever. Samsung is aggressively targeting TSMC and GFI 28nm top customers including AMD, Nvidia, Qualcomm, Broadcom, Marvell, and Xilinx.

Cost and delivery are the key components of a wafer manufacturing contract and Samsung is an expert in both areas. Especially since margins for the Samsung foundry business are not broken out so they could literally dump wafers to get market share. TSMC on the other hand has the biggest wafer margins in the industry which they could cut in half and still make money.

The Samsung cut throat culture is inside the company as well. Multiple Samsung groups compete for a given market. Samsung has phones and tablets based on Nvidia, Qualcomm, and TI processors as well as having their own ARM based processors. They compete in the same way with their largest customer Apple. Apple will purchase close to eightBILLION dollars in parts from Samsung for the iSeries of products this year alone, making Apple Samsung’s largest customer. Samsung is also Apple’s largest competitor and now they are engaged in a mega legal battle which will literally change the face of consumer electronics, believe it.

Even the marketing guys are mixing it up with Samsung firing the first shot:

I’m looking forward to Apple’s response and the Samsung response to that etc…

Let’s not forget the Samsung corruption scandalthat engulfed the government of South Korea. Let’s not forget the chip dumping probes. The book “Think Samsung” by ex-Samsung legal counsel accuses Samsung of being the most corrupt company in Asia.

This battle will be bloody entertaining to say the least! Not so much for GFI though, or the other second source foundries as they see already thinning margins get thinner. For us consumers however it means two things: Semiconductor manufacturing innovation and CHEAP CHIPS! w00t!


Did Apple Influence AMD’s TSMC Foundry Switch?

Did Apple Influence AMD’s TSMC Foundry Switch?
by Ed McKernan on 11-27-2011 at 7:00 pm

During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3 due in 2012 highlight the extent to Apple’s involvement in design and investment to guarantee supply at a much reduced cost so that competitors are left gasping. Turning to the processor world, we know Apple has selected TSMC to Fab their 28nm A6 processor. Why not pull AMD into the Apple-TSMC supply chain ecosystem in order to outmaneuver the raft of Intel based Ultrabook PCs that are headed to the market in 2012?

Continue reading “Did Apple Influence AMD’s TSMC Foundry Switch?”


Physical Verification of 3D-IC Designs using TSVs

Physical Verification of 3D-IC Designs using TSVs
by Daniel Payne on 11-12-2011 at 10:36 am

3D-IC design has become a popular discussion topic in the past few years because of the integration benefits and potential cost savings, so I wanted to learn more about how the DRC and LVS flows were being adapted. My first stop was the Global Semiconductor Alliance web site where I found a presentation about how DRC and LVS flows were extended by Mentor Graphics for the Calibre tool to handle TSV (Thru Silicon Via) technology. This extension is called Calibre 3DSTACK.

With TSV each die now becomes double-sided in terms of metal interconnect. DRC and LVS have to now verify the TSV, plus front and back metal layers.

The new 3DSTACK configuration file controls DRC and LVS across the stacked die:

A second source that I read was at SOC IP where there were more details provided about the configuration file.

This rule file for the 3D stack has a list of dies with their order number, postion of each die, rotation, orientation, location of the GDS layout files and associated rule files and directories.

To do the parasitic extraction requires new information about the size and electrical properties of the microbumps, copper pillars and bonding materials.

One methodology is to first run DRC, LVS and extraction on each die separately, then add the interfaces. The interface between the stacked dies uses a separate GDS, and LVS/DRC checks are run against this GDS.

For connectivity checking between dies text labels are inserted at the interface microbump locations.

With these new 3D extensions then Calibre can run DRC, LVS and extraction on the entire 3D stack. A GUI helps you to visual the 3D rules and results from DRC, LVS and extraction:

TSMC Partner of the Year Award
Based on this extension of Calibre into the 3D realm, TSMC has just announced that Mentor was chosen as the TSMC Partner of the Year. IC designers continue to use the familiar Calibre rule decks with the added 3DSTACK technology.

Summary
Yes, 3D-IC design is a reality today where foundries and EDA companies are working together to provide tools and technology to extend 2D and 2.5D flows for DRC, LVS and extraction.

Further Info

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Synopsys Awarded TSMC’s Interface IP Partner of the Year

Synopsys Awarded TSMC’s Interface IP Partner of the Year
by Eric Esteve on 11-09-2011 at 9:19 am

Is it surprising to see that Synopsys has been selected Interface IP partner of the year by TSMC? Not really, as the company is the clear leader on this IP market segment (which includes USB, PCI Express, SATA, DDRn, HDMI, MIPI and others protocols like Ethernet, DisplayPort, Hyper Transport, Infiniband, Serial RapidIO…). But, looking five years back (in 2006), Synopsys was competing with Rambus (no more active on this type of activity), ARM (still present, but not very involved), and a bunch of “defunct” companies like ChipIdea (bought by MIPS in 2007, then sold to Synopsys in 2009), Virage Logic (acquired by Synopsys in 2010)…At that time, the Interface IP market was weighting $205M (according with Gartner) and Synopsys had a decent 25% market share. Since then, the growth has been sustained (see the picture showing the market evolution for USB, PCIe, DDRn, SATA and HDMI) and Synopsys is enjoying in 2010 a market share of… be patient, I will disclose the figure later in this document!

What we can see on the above picture is the negative impact of the Q4 2008-Q1/Q2/Q3 2009 recession on the growth rate for every segment – except DDRn Memory Controller. Even if in 2010, the market has recovered, we should come back to 20-30% like growth rate only in 2011. What will happen in 2012 depends, as always, of the health of the global economy. Assuming no catastrophic event, 2010/2011 growth should continue, and the interface IP market should reach in 2012 a $350M level, or be 58% larger than in 2009 (a 17% CAGR during these 3 years).

The reasons for growth are well known (at least for those who read Semiwiki frequently!): the massive move from parallel I/Os to high speed serial, the ever increasing need for more bandwidth, not only in Networking, but also in PC, PC peripheral, Wireless and Consumer Electronic segments – just because we (the end user) exchange more data through Emails, Social Media, watch movies or listen music on various, and new, electronic systems. Also because these protocols standards are not falling in commoditization (which badly impact the price you sell Interface IP), as the various organizations (SATA, USB, PCIe, DDRn to name the most important) are releasing new protocol version (PCIe gen-3, USB 3.0, SATA 6G, DDR4) which help to keep high selling price for the IP. For the mature protocols, the chip makers expects the IP vendors to port the PHY (physical part, technology dependant) on the latest technology node (40 or 28 nm), which again help to keep price in the high range (half million dollar or so). Thus the market growth will continue, at least for the next three to four years. IPnest has built a forecast dedicated to these Interface IP segments, up to 2015, and we expect to see a sustained growth for a market climbing to a $400M to $450M range (don’t expect IPNEST to release a 3 digit precision forecast, this is simply anti-scientific!)…

But what about Synopsys’ position? Our latest market evaluation (one week old) integrated in the “Interface IP Survey 2005-2010 – Forecast 2011-2015” shows that for 2010, Synopsys has not only kept the leader position, but has consolidated and has passed from a 25% market share in 2006 to a 40%+ share in 2010. Even more impressive, the company is getting at least 50% more market share (sometime more than 80%) in the segments where they are playing, namely USB, PCI Express, SATA, DDRn, with the exception of HDMI, where Silicon Image is really too strong- on a protocol they have invented, that make sense!

All of the above explains why TSMC has made the good choice, and any other decision would not have been rational… except maybe to decide to develop (or at least market) themselves the Interface IP functions, like the FPGA vendors are doing…

By the way, if you plan to attend IP-SoC 2011 in December 7-8[SUP]th[/SUP] in Grenoble, don’t miss the presentation I will give on the Interface IP market, see the Conference agenda.

Eric Esteve from IPNEST – Table of Contentfor “Interface IP Survey 2005-2010 – Forecast 2011-2015” available here


3D Transistors @ TSMC 20nm!

3D Transistors @ TSMC 20nm!
by Daniel Nenni on 11-06-2011 at 12:51 pm

Ever since the TSMC OIP Forum where Dr. Shang-Yi Chiang openly asked customers, “When do you want 3D Transistors (FinFETS)?” I have heard quite a few debates on the topic inside the top fabless semiconductor companies. The bottom line, in my expert opinion, is that TSMC will add FinFETS to the N20 (20nm) process node in parallel with planar transistors and here are the reasons why:



Eliminating EXCESS:
In the next few years, traditional planar CMOS field-effect transistors will be replaced by alternate architectures that boost the gate’s control of the channel. The UTB SOI

replaces the bulk silicon channel with a thin layer of silicon mounted on insulator. The FinFET turns the transistor channel on its side and wraps the gate around three sides. (Click to enlarge)

The1999 IDM paper Sub 50-nm FinFET: PMOSstarted the 3D transistor ball rolling then in May of 2011 Intel announceda production version of a 3D transistor (TriGate) technology at 22nm. Intel is the leader in semiconductor process technologies so you can be sure that others will follow. Intel has a nice “History of the Transistor” backgrounder in case you are interested. Probably the most comprehensive article on the subject was just published by IEEE Spectrum “Transistor Wars: Rival architectures face off in a bid to keep Moore’s Law alive”. This is a must read for all of us semiconductor transistor laymen.


DOWN AND UP:
A cross section of UTB SOI transistors and a micrograph of an array of FinFET transistors .

Why the push to 3D transistors at 20nm?

Reason #1 is because of scaling. From 40nm to 28nm we saw significant opportunities for a reduction in die size and power requirements plus an increase in performance. The TSMC 28nm gate-last HKMG node will go down in history as the most profitable node ever, believe it! Unfortunately standard planar transistors are not scaling well from 28nm to 20nm, causing a reduction of the power/die savings and performance boost customers have come to expect from a process shrink. From what I have heard it is half what was expected/hoped for. As a result, TSMC will definitely offer 3D transistors at the 20nm node, probably as a mid-life node booster.



Shrinking returns:
As transistors got smaller, their power demands grew. By 2001, the power that leaked through a transistor when it was off was fast approaching the amount of power needed to turn the transistor on , a warning sign for the chip industry. As these Intel data show, the leakage problem eventually put a halt to the transistor scaling , a progression called Dennard’s law. Switching to alternate architectures will allow chipmakers to shrink transistors again, boosting transistor density and performance.

Reason #2 is because TSMC can and it will offer a significant competitive advantage against the second source foundries (UMC, GFI, SMIC). DR. Chenming Hu is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was the Chief Technology Officer of TSMC. Hu coined the term FinFET 10+ years ago when he and his team built the first FinFETs and described them in the 1999 IEDM paper. The name FinFET because the transistors (technically known as Field Effect Transistors) look like fins. Hu didn’t register patents on the design or manufacturing process to make it as widely available as possible and was confident the industry would adopt it. Well, he was absolutely right!

The push for 3D transistors clearly shows that the days of planar transistor scaling will soon be behind us. It also shows what lengths we will go through to continue Moore’s Law. Or as TSMC says “More-than Moore Technologies”.


High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!
by Daniel Nenni on 11-01-2011 at 9:00 am

Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER MOSFET/Analog Switch/ADC/CDA/PLL sold to companies like Fujitsu, Toshiba …etc.

We used to have a project when I worked on R&D to simulate the process based on the device architecture and send the out data to a simulator called PICE which is a device simulator and the output again was sent to the input of Spice simulator , as the Process simulator , the device simulator and spice simulator are connected.

We can easily define the performance of the targeted analog circuit with variation of process recipe and device structures, we can also predict the yield of each corner with running the spice PVT simulation against the six sigmal spice models. However, as you know, the performance always has to compromise with the reliability, and you can’t run the circuit simulation together with the reliability models, because no such models are available.

As a result I do not pay much attention to the result of spice simulation, because it can never tell you what the reliability will be with the result of spice simulation, and I still believe real corner lot wafer is the best way to verify the performance, yield and reliability.

Hi Edward,

Process variation is of great interest at 28nm and even more at 20nm. In a recent independent survey, variation-aware custom IC design was ranked the number one area requiring advancement over the next two years. The survey revealed:

[LIST=1]

  • 53% of design groups missed deadlines or experienced respins due to variation issues
  • Designers experienced an average 2 month delay due to variation issues
  • Designers spent an average 22% of design time on variation issues

    For further information, see the Gary Smith EDA analyst report on variation design.

    Here is a recent webinar done by Solido and TSMC on High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design.

    Attendees of this webinar learned:

    [LIST=1]

  • Variation challenges in custom IC design
  • Variation-aware solutions available in the TSMC AMS reference flow
  • Methods to develop and verify designs over PVT corners in less time
  • How to efficiently apply Monte Carlo techniques in design sign-off
  • How Monte Carlo is really possible up to 6-sigma
  • Customer case studies of the above methods

    Solido customer case studies include:

    [LIST=1]

  • NVIDIA for memory, standard cell, analog/RF design
  • Qualcomm for memory design
  • Huawei-HiSilicon for analog design
  • Qualcomm for I/O design
  • Anonymous for analog/RF design

    Presenters:

    [LIST=1]

  • Nigel Bleasdale, Director of Product Management, Solido Design Automation
  • Jason Chen, Design Methodology and Service Marketing, TSMC

    Audience: Circuit Designers, Design Managers, CAD Engineers