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TSMC versus Intel at 20nm!

TSMC versus Intel at 20nm!
by Daniel Nenni on 04-24-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC
10 Comments

The biggest news out of the TSMC Symposium last week was the 20nm update. Lots of debate and speculation, just why is TSMC releasing one version of 20nm (20nm SoC) versus multiple versions like in 40nm (LP, G, LPG) and 28nm (HP, HPM, HPL, LP)? Here are my thoughts, I would also be interested in your feedback in the comment section. This really is a big change for both TSMC and the foundry business so it is certainly worth discussing.

Morris Chang did a candid interview in early January discussing Intel as a competitor. Morris is a very clever man, a master at the card game bridge, so you can really read a lot into of what he has said here:

“TSMC’s technologies and performance have reached quite a high level, bringing us into contact with different rivals,” Chang said

The high level is volumes of mobile chips, volumes that will certainly rival Intel’s microprocessor business in the not too distant future.

“The competitors we face are Samsung Electronics Co. and GlobalFoundries Inc., with Intel standing ‘behind a veil’ because it is a rival against many of our customers,” Chang said, adding that these TSMC customers include integrated circuit designers and integrated device manufacturers.

The strategic positioning begins! TSMC is a pure-play foundry and collaborates with customers versus IDMs (Intel/Samsung) that competes with customers. The Apple/Samsung legal drama is a glaring example of this.

At the Symposium, Morris mentioned R&D expenses of TSMC versus Intel and Samsung, the difference being, TSMC collaborates with customers/partners and leverages R&D expenses. So the equation looks like this:

Top 10 TSMC customers R&D expenses + TSMC R&D expenses > Intel + Samsung R&D expenses

Another interesting quote from the article:

Samsung and GlobalFoundries are newcomers in the industry, Chang said, and suggested that TSMC’s customers should diversify their foundry sources rather than rely on TSMC only.

Which is interesting advice coming from the Chairman of TSMC. It is certainly a message to TSMC employees that second source competition is always a threat so even with 50%+ market share there is no time to rest on previous accomplishments. Notice he does not mention Intel here. Of course Morris followed that quote with something of purpose:

“All of our customers rely on TSMC in foundry production, and Intel relies on its own foundry plants,” he said. “If our technologies are not improved enough and Intel keeps improving its technologies, our customers’ products will lose competitiveness to those of Intel. It’s horrible to imagine the outcome.”

Another competitive shot at Intel! Well played Mr Chairman. I wish I could use a bridge analogy here but I don’t play bridge. Morris ended the interview with another shot at Intel:

“TSMC will stand behind our customers and cooperate with them. The battlefield between our customers and Intel is where we compete against Intel,” he added.

So it is the fabless companies, ARM, and TSMC against Intel. I like those odds!

Back to 20nm. Intel has one version of 22nm so to better compete with Intel TSMC will focus all resources on a single SoC optimized version of 20nm, simple as that. TSMC may also offer FinFets at 20nm so customers will have a choice between planar and FinFet transistor implementations, something that Intel does not offer. It is also about capacity. TSMC’s CAPEX hike is all about 20nm and with one S0C optimized version there won’t be the shortages we see at 28nm.

Sound reasonable? Please use the comment section for further analysis.

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Qualcomm Meets Jerry Sanders at 28nm

Qualcomm Meets Jerry Sanders at 28nm
by Ed McKernan on 04-19-2012 at 8:26 pm
Categories: Foundries, Intel Foundry, TSMC
9 Comments

First the good news: 4G LTE design in activity is off the charts as OEMs building smartphones, tablets and Ultrabooks are buying into the capability for product rollouts that will occur starting in September. Now the bad news: there’s not enough to go around until probably well into 2013. For a Company sitting on over $26B in cash, twice as much as Intel, this is a disaster that didn’t have to happen. Now Qualcomm is in panic mode, as it must spend engineering resources and dollars taping out designs to alternative fabs (likely Global Foundries and Samsung). For this misstep, they will probably pay the price of throttling back the 28nm Snapdragon design win effort and hand over market share to Intel.

As mentioned in previous blogs that I have written, there really are only four players left in the semiconductor game outside of memory. It’s Intel, Samsung, Apple and Qualcomm. Of the four, Qualcomm has played the most risk-averse game of poker, not willing to make bets beyond a single penny ante. Qualcomm was satisfied for many years as TSMC’s largest customer, what could go wrong. Plenty. Like having to share the same leading edge factory capacity several times over with other sizeable fabless players (i.e. Altera, Xilinx, nVidia and Broadcom) including some who are your leading and future competitors.

TSMC can’t be faulted for tallying up every customers wafer forecast and dividing by three, four or even five to get to some reasonable expected market demand. But then nobody expected the “end of the world” economic situation in 2008-2009 followed by the Apple driven Mobile Tsunami of iPhones and iPADs that drove right through the downturn. Apple, though, had its supply chain covered with well-managed capacity build outs at Samsung and Toshiba. Vertical Integration is where we are at and Qualcomm is the only one who hasn’t figured it out.

Intel overbuilt on 22nm capacity knowing that a circuit breaker was going to trip with all their competitors tied into the same single Fab source called TSMC. Malcolm Penn of Future Horizons has a great pitch on this, which I highly recommend. The only way to avoid this trap is to return to the Jerry Sanders Real Men Have Fabs strategy. It is the way in which Qualcomm can break away from Broadcom, Marvell and Mediatek. It also is the only way Qualcomm has a shot of going mano-on-mano with Intel as the end game plays out these next 3-5 years.

Intel’s greatest leaps forward, as I witnessed in the 1990s , was when their competitors screwed up during the moment that they were making their own transition to a new process with a new product. The market jumped on the new product in a stepped function manor and demand went through the roof. Everything a day old was immediately obsolete rotting in the channels. I am thinking about the transition from Pentium to Pentium MMX in the mid 1990s as an example.

In the earnings conference call, there was a moment when Steven Mollenkopf, President and COO of Qualcomm said: “Now in some cases also, our OEM partners are, of course, working with us very closely to try to help us accelerate our own supply.” I take this to mean Apple is stepping in to open doors at Samsung in order for Qualcomm to tape out a part that will only go in the iPhone 5. It is a weak position to be in when your customer is needed to open the doors to new capacity. This is likely to be paid back with a pound of flesh.

For those who a year ago thought that the ARM camp was on its way to dethroning Intel and all the pieces were in place, it is time to adjust to the reality that having a Fab Matters, now more than ever. Qualcomm, at roughly half the sales of Intel needs to write a $5B check for a New Fab starting immediately.

FULL DISCLOSURE: I am long AAPL, INTC, QCOM and ALTR

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Introduction to FinFET technology Part I

Introduction to FinFET technology Part I
by Tom Dillinger on 04-18-2012 at 6:00 pm
Categories: FinFET, Foundries, Intel Foundry, TSMC

This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers. These articles will highlight the technology’s key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication, modeling, and the resulting impact upon existing EDA tools and flows. (And, of course, feedback from SemiWiki readers will certainly help influence subsequent topics, as well.)

Scaling of planar FET’s has continued to provide performance, power, and circuit density improvements, up to the 22/20nm process node. Although active research on FinFET devices has been ongoing for more than a decade, their use by a production fab has only recently gained adoption.

The basic cross-section of a single FinFET is shown in Figure 1. The key dimensional parameters are the height and thickness of the fin. As with planar devices, the drawn gate length (not shown) separating the source and drain nodes is a “critical design dimension”. As will be described in the next installment in this series, the h_fin and t_fin measures are defined by the fabrication process, and are not design parameters.


Figure 1. FinFET cross-section, with gate dielectric on fin sidewalls and top, and bulk silicon substrate
The FinFET cross-section depicts the gate spanning both sides and the top of the fin. For simplicity, a single gate dielectric layer is shown, abstracting the complex multi-layer dielectrics used to realize an “effective” oxide thickness (EOT). Similarly, a simple gate layer is shown, abstracting the multiple materials comprising the (metal) gate.

In the research literature, FinFET’s have also been fabricated with a thick dielectric layer on top, limiting the gate’s electrostatic control on the fin silicon to just the sidewalls. Some researchers have even fabricated independent gate signals, one for each fin sidewall – in this case, one gate is the device input and the other provides the equivalent of FET “back bias” control.

For the remainder of this series, the discussion will focus on the gate configuration shown, with a thin gate dielectric on three sides. (Intel denotes this as “Tri-Gate” in their recent IvyBridge product announcements.) Due to the more complex fabrication steps (and costs) of “dual-gate” and “independent-gate” devices, the expectation is that these alternatives will not reach high volume production, despite some of their unique electrical characteristics.

Another fabrication alternative is to provide an SOI substrate for the fin, rather than the bulk silicon substrate shown in the figure. In this series, the focus will be on bulk FinFET’s, although differences between bulk and SOI substrate fabrication will be highlighted in several examples.



Figure 2. Multiple fins in parallel spaced s_fin apart, common gate input

Figure 2 illustrates a cross-section of multiple fins connected in parallel, with a continuous gate material spanning the fins. The Source and Drain nodes of the parallel fins are not visible in this cross-section – subsequent figures will show the layout and cross-section view of parallel S/D connections. The use of parallel fins to provide higher drive current introduces a third parameter, the local fin spacing (s_fin).

Simplistically, the effective device width of a single fin is: (2*h_fin + t_fin), the total measure of the gate’s electrostatic control over the silicon channel. The goal of the fabrication process would be to enable a small fin spacing, so that the FinFET exceeds the device width that a planar FET process would otherwise provide:

s_fin < (2*h_fin + t_fin)

Subsequent discussions in this series will review some of the unique characteristics of FinFET’s, which result in behavior that differs from the simple (2*h + t) channel surface current width multiplier.

The ideal topology of a “tall, narrow” fin for optimum circuit density is mitigated by the difficulties and variations associated with fabricating a high aspect ratio fin. In practice, an aspect ratio of (h_fin/t_fin ~2:1) is more realistic.

One immediate consequence of FinFET circuit design is that the increments of device width are limited to (2h + t), by adding another fin in parallel. Actually, due to the unique means by which fins are patterned, a common device width increment will be (2*(2h+t)), as will be discussed in the next installment in this series.

The quantization of device width in FinFET circuit design is definitely different than the continuous values available with planar technology. However, most logic cells already use limited device widths anyway, and custom circuit optimization algorithms typically support “snapping” to a fixed set of available width values. SRAM arrays and analog circuits are the most impacted by the quantized widths of FinFET’s – especially SRAM bit cells, where high layout density and robust readability/writeability criteria both need to be satisfied.

The underlying bulk silicon substrate from which the fin is fabricated is typically undoped (i.e., a very low impurity concentration per cm**3). The switching input threshold voltage of the FinFET device (Vt) is set by the workfunction potential differences between the gate, dielectric, and (undoped) silicon materials.

Although the silicon fin impurity concentration is effectively undoped, the process needs to introduce impurities under the fin as a channel stop, to block “punchthrough” current between source and drain nodes from carriers not controlled electrostatically by the gate input. The optimum means of introducing the punchthrough-stop impurity region below the fin, without substantially perturbing the (undoped) concentration in the fin volume itself, is an active area of process development.

Modern chip designs expect to have multiple Vt device offerings available – e.g., a “standard” Vt, a “high” Vt, and a “low” Vt – to enable cell-swap optimizations that trade-off performance versus (leakage) power. For example, the delay of an SVT-based logic circuit path could be improved by selectively introducing LVT-based cells, at the expense of higher power. In planar fabrication technologies, multiple Vt device offerings are readily available, using a set of threshold-adjusting impurity implants into masked channel regions. In FinFET technologies, different device thresholds would be provided by an alternative gate metallurgy, with different workfunction potentials.

The availability of multiple (nFET and pFET) device thresholds is a good example of the tradeoffs between FinFET’s and planar devices. In a planar technology, the cost of additional threshold offerings is relatively low, as the cost of an additional masking step and implant is straightforward. However, the manufacturing variation in planar device Vt’s due to “channel random dopant fluctuation” (RDF) from the implants is high. For FinFET’s, the cost of additional gate metallurgy processing for multiple Vt’s is higher – yet, no impurity introduction into the channel is required, and thus, little RDF-based variation is measured. (Cost, performance, and statistical variation comparisons will come up on several occasions in this series of articles.)

The low impurity concentration in the fin also results in less channel scattering when the device is active, improving the carrier mobility and device current.

Conversely, FinFET’s introduce other sources of variation, not present with planar devices. The fin edge “roughness” will result in variation in device Vt and drive current. (Chemical etch steps that are selective to the specific silicon crystal surface orientation of the fin sidewall are used to help reduce roughness.)

The characteristics of both planar and FinFET devices depend upon Gate Edge Roughness, as well. The fabrication of the gate traversing the topology over and between fins will increase the GER variation for FinFET devices, as shown in Figure 3.



Figure 3. SEM cross-section of multiple fins. Gate edge roughness over the fin is highlighted in the expanded inset picture. From Baravelli, et al, “Impact of Line Edge Roughness and Random Dopant Fluctuation on FinFET Matching Performance”, IEEE Transactions on Nanotechnology, v.7(3), May 2008.

The next entry in this series will discuss some of the unique fabrication steps for FinFET’s, and how these steps influence design, layout, and Design for Manufacturability:

Introduction to FinFET technology Part II

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Atrenta’s Spring Cleaning Deal

Atrenta’s Spring Cleaning Deal
by Paul McLellan on 04-16-2012 at 9:00 am
Categories: EDA, Foundries, TSMC

Atrenta is having a special offer to let you “spring clean” your IP for free. They are providing two weeks of free access to the Atrenta IP kit starting from today, April 16th, until the end of May. During this period, qualified design groups in the US will be able to use the kit for two consecutive weeks to “spring clean” their third party or internally developed IP blocks at no cost.

Atrenta’s IP Kit is also used by TSMC to quality soft IP for inclusion in the TSMC 9000 IP library. See my blog here. Plus it is TSMC’s technology symposium tomorrow.

The IP Kit generates two important reports: the Atrenta DashBoard and DataSheet.


The Atrenta DashBoard provides a pass/fail status for all IP blocks. It shows the status of the block for key design objectives such as CDC, power, test, timing constraints and more. It also reflects overall readiness of the IP as measured by various quality goals. User-defined success criteria are used to report tolerance to fatals, errors and warnings. Designers are able to drill down to get additional information on the exact violations reported, as well as access trend data that shows overall progress to achieve a passing status over time. A SpyGlass Clean report has no failures reported.


The second report is the Atrenta DataSheet. This report focuses on IP characteristics. Once the DashBoard report is “clean,” the DataSheet acts as a final handoff document that captures key information about the IP block, such as the I/O table, clock trees, reset trees, final power spec, test coverage, constraints coverage and more. Especially useful when a block is being integrated, the report gathers this key information into one easy-to-read HTML document.

And if you really get carried away with the idea of spring cleaning, my condo could do with some attention.

Details on the IP Kit Spring Cleaning promotion is here.

And Atrenta’s geek friend has his own take (1.5 mins):

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Making your ARMs POP

Making your ARMs POP
by Paul McLellan on 04-16-2012 at 6:30 am
Categories: Arm, Foundries, IP, TSMC

Just in time for TSMC’s technology symposium (tomorrow) ARM have announced a whole portfolio of new Processor Optimization Packs (POPs) for TSMC 40nm and 28nm. For most people, me included, my first question was ‘What is a POP?’

A POP is three things:

  • physical IP
  • certified benchmarking
  • implementation knowledge

Basically, ARM takes their microprocessors, which are soft cores, and implements them. Since so many of their customers use TSMC as a foundry, the various TSMC processes are obviously among the most important. They examine the critical paths and the cache memories and design special standard cells and other elements to optimally match the processor to the process. They don’t do this just once, they pick a few sensible implementation choices (highest performance 4 core for networking, medium performance dual core for smartphones, lowest power single core for low end devices). A single POP contains all the components necessary for all these different power/performance/area points. Further, although we all casually say things like ‘TSMC 40nm’ in fact TSMC has two or three processes at each node to hit different performance/power points, so they have to do all of this several times.

Then they provide the performance benchmarks that they managed to achieve, along with all the detailed implementation instructions as to how they did it. These are EDA tool chain independent since customers have different methodologies. But the combination of IP and documentation should allow anyone to reproduce their results or get equivalent results with their own implementations after any changes that they have made for their own purposes and to differentiate themselves from their competitors.

Companies using the POPs get noticeably better results than simply using the regular libraries and doing without the specially optimized IP.

About 50% of licensees of the processors for which POPs have been available seem to have licensed them, currently there are 28 companies using them. Here’s a complete list of the POPs (click to enlarge):
Of course ARM has new microprocessors in development (for example, the 64 bit ones already announced) and they are also working closely with foundries at 20nm and 14nm (including FinFETs). So expect that when future microprocessors pop out that a POP will pop out too.

About TSMC
TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 470 customers and manufactured more than 8,900 products for various applications covering a variety of computer, communications and consumer electronics market segments. Total capacity of the manufacturing facilities managed by TSMC, including subsidiaries and joint ventures, reached above 9 million 12-inch equivalent wafers in 2015. TSMC operates three advanced 12-inch wafer GIGAFAB™ facilities (fab 12, 14 and 15), four eight-inch wafer fabs (fab 3, 5, 6, and 8), one six-inch wafer fab (fab 2) and two backend fabs (advanced backend fab 1 and 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited, In addition, TSMC obtains 8-inch wafer capacity from other companies in which the Company has an equity interest.

TSMC’s 2015 total sales revenue reached a new high at US$26.61 billion. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea.

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The Truth of TSMC 28nm Yield!

The Truth of TSMC 28nm Yield!
by Daniel Nenni on 04-15-2012 at 7:00 pm
Categories: Foundries, TSMC

As I write this I sit heavyhearted in the EVA executive lounge returning from my 69[SUP]th[/SUP] trip to Taiwan. I go every month or so, you do the math. This trip was very disappointing as I can now confirm that just about everything you have read about TSMC 28nm yield is absolutely MANURE!
Continue reading “The Truth of TSMC 28nm Yield!”

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Intel’s Fait Accompli Foundry Strategy

Intel’s Fait Accompli Foundry Strategy
by Ed McKernan on 04-05-2012 at 1:09 am
Categories: Foundries, FPGA, Intel Foundry, TSMC

As many analysts have noted, it is difficult to imagine what Intel’s foundry business will look like one, two or even three years down the road because this is all new and what leading fabless player would place their well being in the hands of one who is totally new at the game. I would like to suggest there is a strategy in place that will soon lead to tectonic shifts in the semiconductor world. The assembled pieces of “no-name” startup chip companies building in Intel’s advanced 22nm trigate process include Achronix, Tabula and now Netronome. Each represent three possible solutions to high performance data path processing that may lead to Intel’s goal of dominance in the combined server, storage, networking platform. Or, perhaps they may serve as a forcing function for leading Altera, Xilinx, Broadcom, Marvell or Cavium away from TSMC and partnering with Intel. Either outcome is a win for Intel.

For much the past three years the spotlight has shined brightly on everything that is mobile – as it should have. Questions about Intel’s ability to either counter Apple’s ARM based mobile rise or to be its eventual supplier across the board will be on every analysts mind until there is resolution. However, there is another side to Intel’s business that is not well understood. Intel always fights a multi-front war to maximize its advantage and overwhelm competitors without similar magnitudes of resources. Only Intel, historically, has been able to do this.

Today, while it charges ahead with its Medfield processor in the smartphone and tablet space to blunt ARM’s early lead, Intel enters a mopping up phase in the PC market with its Ivy Bridge based Ultrabooks that will neuter AMD and nVidia in what will be the highest volume segment by the end of 2013. And in the background Intel has opened up a third front against the foundries of TSMC, Global Foundries and Samsung who the ARM Camp depends on to win the Mobile Tsunami Marketplace. Without a process within spitting distance of Intel, ARM would be relegated to trailing edge embedded SOCs. Therefore Intel will leverage its Fabs to peel away Foundry customers, cutting off oxygen that pays for future capital expenditures at leading nodes.

The announcements that FPGA startups Achronix and Tabula are utilizing Intel’s 22nm process technology had some guessing where were Xilinx and Altera. With Netronome, the question could be where is Cavium and the Netlogic RMI group acquired by Broadcom. All attack the data processing path that Intel needs to fill out the networking platform. The acquisition of Fulcrum last summer and QLogic’s Infiniband group provide critical functions that should be able to leverage 22nm at the expense of Broadcom and Marvell’s switch chips and Mellanox Infiniband chips.

As Andy Bechtolsheim, the former Sun founder and Google investor and now running Arista, a startup building low-latency high performance switches, said the era of ASIC based switch chips is over. The inevitable march towards merchant Ethernet silicon is on and who can build the fastest chips accessing the latest technologies wins. The Fulcrum acquisition seems to preclude Broadcom and Marvell from a Foundry slot unless they were to sign away product rights.

Traction by Achronix or Tabula could force Xilinx or Altera to seek an entry into the 22nm trigate process. Until now, both Xilinx and Altera have walled off the FPGA market to startups with their software tools, leading edge processes and robust IP. However what happens if a startup competitor gets a 3-year process technology advantage. In 2009, Altera beat Xilinx out the door by 12 months with its high end 40nm Stratix IV and ended up crushing them in the communications space, a segment that represents almost half the revenue and the majority of the profits. You have to wonder if there is any reason that they aren’t both running test wafers at Intel.

Diminishing nVidia and AMD’s stature in the PC and tablet business; pulling away a Xilinx or Altera; outrunning Broadcom and Marvell in the switch chip market all seem to be part of an overriding strategy that has yet to be communicated by Intel but is a factor in their massive capital expenditure that looks to double capacity by the end of 2013 and put some distance between them and the Foundries. If Intel out executes on the process side, then many fabless vendors may be presented with a Fait Accompli.


FULL DISCLOSURE: I am long INTC, AAPL, ALTR, QCOM

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NVIDIA Claims TSMC 20nm will not Scale?

NVIDIA Claims TSMC 20nm will not Scale?
by Daniel Nenni on 03-25-2012 at 6:00 pm
Categories: Foundries, TSMC

Interesting article from Joel Hruska on ExtremeTech: Nvidia deeply unhappy with TSMC, claims 22nm essentially worthless . The title is a bit dramatic (poetic license) but the charts are accurate to the degree that 20nm costs will be significantly higher from the start and will continue to be higher throughout production and maturity.

One reason is double patterning, which is required at 20nm (double patterning splits a design into separate masks when devices are too close together). If 28nm masks cost $3M, 20nm masks will cost $5M or more. Another reason is design complexity: layout dependent effects (LDE) and process variation will get worse at 20nm, simulation and verification requirements will explode, and the list goes on…

Life in the semiconductor ecosystem certainly gets more complicated when you try and cram 30B+ planar transistors on one chip, absolutely!

There is no doubt in my mind that these slides are authentic. NVIDIA CEO Jen-Hsun is quite the showman and has a reputation for this kind of public grandstanding. I was a little surprised that NVIDIA used some sort of “normalized” $$$/transistor as a key metric, rather than more traditional semiconductor scaling measures, but perhaps that’s part of their internal business model.

One thing you must know, Jen-Hsun Huang and Morris Chang are VERY close, so you have to play a game of chess here and ask yourself what the agenda really is. A public whipping such as that? Openly criticizing your good friend and founding business partner?

Check out this video at the Silicon Valley Computer Museum, Jen-Hsun interviews Morris, it starts at 8:30 minutes in:

This video will give you a good understanding of the relationship between Jen-Hsun and Morris. It also provides a candid view of Jen-Hsun’s personality, which seems somewhat narcissistic to me.

This topic is certainly timely since the annual TSMC 2012 Technical Symposiumwill take place on April 17[SUP]th[/SUP] at the San Jose Convention Center. Trust me, you’re not going to want to miss this one!

Join the 18th annual TSMC Technology Symposium and get first-hand updates on TSMC’s advanced and specialty technologies, advanced backend capabilities and future development plans!!

  • TSMC’s 20nm and 14nm process development status including FinFet and advanced lithography insights
  • TSMC’s New High-Speed Computing, Mobile Communications, and Connectivity & Storage technology development
  • TSMC’s robust Specialty Technology portfolio that includes Backside Illumination (BSI), Embedded Flash Power IC and MEMS
  • TSMC’s new and exciting GIGAFAB™ new programs and improvements that enhance time-to-volume
  • TSMC’s advanced backend technology for 3D-IC, CoWoS (Chip on Wafer on Substrate), and Bump on Trace (BOT)

To me this is a simple case of wafer pricing negotiations gone wild. Since TSMC is in such a dominant position at 28nm and 20nm the industry is telling them, in the Year of the Dragon, to be more like a teddy bear and collaborate on pricing in the same way they collaborate on technology.

But it’s ridiculous for any fabless semiconductor company to say that they will not aggressively transition to the coming process nodes (20nm and 14nm)! I remember back in the day buying an AMD 40MHZ based PC versus an Intel 36MHZ. Seriously, did I really need that extra 4MHZ? Did I pay extra for it? Of course!

At AMD’s Financial Analyst Day, CEO Rory Read made a point of saying that the company no longer intends to aggressively transition to new process nodes given the diminishing marginal returns from doing so.…….

Okay, let me clarify, any leading edge fabless semiconductor company that wants to STAY in business will aggressively transition to the coming semiconductor nodes, absolutely. Just my opinion of course.

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TSMC absolutely did NOT halt 28nm production!

TSMC absolutely did NOT halt 28nm production!
by Daniel Nenni on 03-07-2012 at 6:18 pm
Categories: Foundries, TSMC

Once again industry professionals get duped! Tabloid journalism runs amok inside the semiconductor ecosystem! As if our industry does not face enough challenges, why are we wasting time on drivel like this? This is a TSMC 28nm wafer by the way and thousands of them are being shipped around the world, believe it.
 Continue reading “TSMC absolutely did NOT halt 28nm production!”