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September 23, 2014

The TSMC iPhone 6!

The TSMC iPhone 6!
by Daniel Nenni on 09-23-2014 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

Fortunately Paul McLellan and I missed IDF. Paul was atop Mt. Kilimanjaro and I was in Taiwan signing books. After reviewing the materials and watching the videos we really didn’t miss much in regards to mobile so no regrets. The Apple event would have been fun even though I won’t be buying an iPhone6 or an iWatch and I will tell you why.

In case you missed it, the first iPhone 6 tear down is up on iFixit and surprise-surprise it is filled with silicon from TSMC’s customers (Apple A8, Qualcomm: modem, PM IC – RF transiever – LTE receive and envelope tracking, Murata wifi module, Broadcom touchscreen controller, NXP NFC, and chips from Skyworks, InvenSense, Avago and TriQuint). The absence of Samsung silicon was not a surprise however and it supports my theory that, given the choice, fabless companies will partner with pure-play over IDM foundries, absolutely. The fact that Samsung and Apple have intellectual property issues and Samsung has constant anti Apple advertisements probably does not help either but that comes with competing with your customers I suppose.

Intel’s 35% Density Advantage Claim Explored

Intel’s 35% Density Advantage Claim Explored
by Daniel Nenni on 09-20-2014 at 1:00 pm
Categories: Foundries, Intel Foundry, TSMC

The previous blog I did on the density difference between Intel 14nm and TSMC 20nm caused quite a stir and many interesting comments which I would like to address. After writing thousands of blogs on a wide variety of topics I have found that playing the devil’s advocate stimulates the most productive conversations and in this case it proved to be true. The Intel Core M vs Apple A8! blog went viral last week and resulted in some very interesting points made in the comment section that I feel should be explored in greater detail.

First is how we measure density. The semiconductor industry is all about packing more transistors in a smaller space. It is part of Moore’s Law, it is how we get less expensive consumer electronics, it is a badge of honor really. There are two transistor numbers you can use: the number of transistors in a design schematic and the number of transistors in the final layout which is then manufactured. The difference between these numbers varies but after taking a quick poll amongst leading edge design and layout people the range is 0-10% more transistors in the layout. Since density is a badge of honor most companies use the layout transistor count but if it serves a marketing purpose they will use the schematic transistor count. Either way, considering the point I’m trying to make, it doesn’t really matter.

Second, comparing the Intel Core M processor and the Apple A8 SoC is like comparing an orange to an apple but this is the only data we have today and it is a good starting point for a density discussion. The architectures are different (CPU vs SoC), the processes are different (20nm planar vs 14nm FinFET), and the companies are very different (IDM versus Fabless).

Third, the performance, power, and functionality of the chips are not part of this discussion. Tear downs and third party benchmarks will be required and they are not available yet. When they are, we can look back on this discussion and see if we were right and if not we can see where we went wrong. All in the interest of science, right?

Here is the argument: Intel claimed a 35% density advantage over TSMC during their November 2103 Investor Meeting using the middle slide above. Intel also used the Altera slide as support for their claim. TSMC rebuffed that claim during a quarterly conference call using the slide on the left.

According to Apple the A8, which is manufactured by TSMC on a 20nm planar process, has about 2B transistors on a 89mm2 die. According to Intel the Core M manufactured on a 14nm FinFET process has about 1.3B transistors on an 82mm2 die.

Given that:

[LIST=1]

According to TSMC, 16nmFF+ has a 15% density advantage over 20nm planar

We do not know what type of transistor count Intel and Apple uses but assume the worst case with a 10% variance (upsize Intel by 10%)

Intel’s 35% density advantage claim just does not hold up, not even close. Time will tell, silicon does not lie, but for now TSMC’s density slide is much more honorable than Intel’s. And let’s not forget that Intel’s processes are highly specialized for a single product and TSMC’s processes serve a much wider range of applications. If true, this lack of density gap is really big news for the fabless semiconductor ecosystem, absolutely!

TSMC OIP: Registration Open

TSMC OIP: Registration Open
by Paul McLellan on 09-06-2014 at 9:00 am
Categories: Foundries, TSMC

It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event. More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

Registration is now open.

The schedule is as follows:

8.00: registration opens
9.00: welcome remarks
9.20: industry overview and corporate updates
9.50: TSMC and the ecosystem for innovation
10.15: feature talk with ARM
10.45: coffee break

Then at 11am the forum splits into 3 parallel tracks: an EDA track, an IP track and an EDA/IP/services track. There will be a break for lunch from 12pm to 1pm. Many of the presentations feature both a design partner of TSMC and an EDA or IP partner. Several of the presentations are on 16FF and 10FF, so this is an opportunity to hear about the experience of TSMC’s partners on the most advanced nodes. In particular, from 4pm until the end of the afternoon on the EDA track Cadence will be talking about various aspects of 16FF and 10FF design. Synopsys and Mentor are also presenting on aspects of 16FF.

The EDA track features presentations from:

AMCC/Cadence
Synopsys (several)
Qualcomm/Mentor
Cadence (several)
Mentor/TSMC
Mediatek/Synopsys

The IP track features presentations from:

Semtech/Snowbush
GUC
ARM
Kilopass
Cadence
CEVA
ARM (several)
Imagination
Synopsys

The EDA/IP/services track features presentations from:

GUC
Lorentz/Altera
eSilicon
Synopsys
Uniquify
Oracle/Mentor
ANSYS (Apache)
Analog bits
M31 Technology
Microchip SSTI

The day concludes with a social hour from 5.30pm to 6.30pm.

If you are doing design with TSMC (and its almost a case of who isn’t?), and especially if you are about to start on a 16FF design, then you should definitely plan to attend. I think the agenda contains a wealth of interesting sounding experience from design groups working right on the bleeding edge.

Full details of the agenda are here. Registration is here.

Granite River Labs and TSMC Expand Agreement

Granite River Labs and TSMC Expand Agreement
by Paul McLellan on 08-28-2014 at 7:01 am
Categories: Foundries, TSMC

For several years now, TSMC has run increasingly sophisticated IP validation. Ramping a new process as a foundry requires a number of things to all come together almost simultaneously: the process, of course, and some designs to run and start to recover the huge capital investment a modern fab entails. With many SoCs having over a hundred IP blocks, getting the IP qualified is an essential part of a design team being able to get a design into production. Taking a systematic approach to IP quality is paramount for successful SoC products.

TSMC’s latest IP validation has multiple steps, increasingly expensive to execute but with increasing confidence level in the IP. The first 3 steps are a review of the IP without manufacturing it. The later steps involve running extensive tests on IP that has been manufactured, typically in a shuttle run for a new process that is not yet in volume production. For more mature processes where a lot of IP has been in use for many years, the sheer number of designs in successful volume production is its own guarantee of IP quality.

[LIST=1]

Physical review (DRC, LVS, ERC, antenna checks)

DFM compliance (DFM-LPE, LPC, dummy fill, VCMP)

Pre-silicon assessment (design kit review, design review)

Silicon assesment (tapeout review, silicon report review)

Split lot silicon assessment (split lot tapeout and report review)

IP Validation Center (audit IP testing results by TSMC test lab)

Volume production

Last month, TSMC’s IP Validation Center and Granite River Labs deepened their relationship and further expanded the TSMC9000 IP validation ecosystem. This covers expanded test capacity, test auditing and posting IP validation results on TSMC-online. This is a part of item #6 above, leveraging the expertise of GRL in the test and validation of high speed interfaces.

GRL will serve as an IP validation partner to TSMC. The test methodology development and correlation will be done at GRL’s office in Hsinchu (where TSMC is headquartered of course). The bulk of the work will be carried out at GRL in Santa Clara and Bangalore. TSMC will subcontract to GRL to create a test methodology for the specific PHY. GRL can then use their extensive expertise and wide range of costly equipment to perform the testing. The results will then be available through TSMC-online like where it can be searched by potential users.

GRL has extensive electrical test facilities using Introspect, Teledyne Lecroy, Tektronix, Keysight and others. They also hav protocol test solutions that can handle error injection, stress testing, protocol exerciser automation and so on. They have R&D sites in Oregon and Japan. Labs in Santa Clara, Bangalore, Penang, Hsinchu and Taipei. The Asian HQ is in Singapore, worldwide HQ is in Silicon Valley.

When TSMC advocates FD-SOI…

When TSMC advocates FD-SOI…
by Eric Esteve on 08-14-2014 at 1:00 pm
Categories: FD-SOI, Foundries, STMicroelectronics, TSMC

I found a patent recently (May,14 2013) granted to TSMC “Planar Compatible FDSOI Design Architecture”, the following sentences, directly extracted from this patent, advertise FDSOI design better than a commercial promotion! “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.” Nothing new here for Semiwiki readers… except that this enumeration of the advantages of SOI technology in respect with bulk planar is coming from TSMC…

In fact, the sentence mention “SOI substrates”, but when you look at the next paragraph, you find the definition of partially-depleted (PD) SOI transistor and fully-depleted (FD) SOI transistor, and their respective behavior and advantages:

A PDSOI transistor is formed in an active region with an active layer thickness that is larger than the maximum depletion width. The PDSOI transistor therefore has a partially depleted body. PDSOI transistor have the merit of being highly manufacturable, but they suffer from floating body effects. Digital circuits, which typically have higher tolerance for floating body effects may employ PDSOI transistors.
A FDSOI transistor is formed in an active region with an active layer thickness that is smaller than the maximum depletion width. FDSOI transistors avoid problems of floating body effects with the use of a thinner active layer thickness or a lighter body doping. Generally, analog circuitry performs better when designed using FDSOI devices than using PDSOI devices.

To illustrate this patent, TSMC is referring to a Baseband IC for mobile application, or maybe an integrated BB and Application Processor. In both cases many of the integrated IP, like memory cell or high speed SerDes, are based on analog circuitry, thus FDSOI clearly appears to be the best choice.

You may wonder why TSMC is highly promoting FDSOI, as we know that the foundry has not selected this technology. TSMC is supporting 28nm bulk planar, then 20nm (including double patterning for critical layers) and 16nm FinFET. So, why TSMC is doing such an advertising for FDSOI? Reading further, we can see:

“An FDSOI ASIC design in the same footprint as a bulk planar ASIC design provides several advantages over the bulk planar ASIC design. Adaptive body bias techniques are inefficient with bulk planar designs because of the PN junction forward bias issue and because junction leakage increases in the reverse bias condition. Therefore, planar technologies have to adopt voltage scaling techniques for power savings in single Vt designs.”

It look like that TSMC is willing to demonstrate that a FDSOI design can be portable to a bulk planar technology, providing that the power rails have been carefully designed, and this requirement is extensively described within the patent (in fact, it’s the core of the patent). We have highlighted in Semiwiki one of the important advantages linked with FDSOI technology: a dual Vt library can support a complete SoC design, allowing cost savings (number of masks and process steps is lower) and faster process turnaround time, when compared with four Vt on bulk planar, only bulk option to offer the same level of power savings than FDSOI.

But we still don’t know why TSMC has filled this patent. Is it because the company is willing to offer FDSOI as an additional process option to existing customers? In this case, this patent could be a way to minimize risk, showing to a customer moving to FDSOI that he could decide to come back to a bulk planar option, with no redesign because the “FDSOI ASIC design is in the same footprint as a bulk planar ASIC design”. By the way, TSMC offering FDSOI process option would be a scoop…

Another possibility would be that TSMC is not willing to support FDSOI, but certain existing ASIC customer willing to try FDSOI with TSMC competition, this patent would allow TSMC to keep the door opened, and these customers could come back to bulk planar ASIC processed at TSMC. This approach would be like a double sourcing, but between bulk planar and FDSOI.

TSMC has certainly carefully looked at FDSOI as a technology option, even if so far the company doesn’t support FDSOI. I am happy to see that a TSMC patent highlights the many technical advantages of FDSOI vs bulk planar, like absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance. In this advantage list, we can add potential cost savings (when SOI wafer price will go down), faster wafer fab cycle time and probably the most important, far better power efficiency, whether the SoC is designed for Networking infrastructure or mobile application processor. Will all these advantages be enough to compensate some current weaknesses, like customer fear in front of innovation and work in progress IP ecosystem, and finally pushing TSMC to join the ST and Samsung train?

From Eric Esteve from IPNEST

Intel Versus TSMC 14nm Processes

Intel Versus TSMC 14nm Processes
by Scotten Jones on 08-13-2014 at 5:00 pm
Categories: Foundries, Intel Foundry, TSMC

Intel has begun to release some details on their 14nm process. I thought it would be interesting to contrast what Intel has disclosed to TSMC’s 16nm process disclosure from last year’s IEDM (TSMC calls their 14nm process 16nm).

There are both similarities and differences between the processes. Intel’s process is for MPUs and TSMC’s process is for SOCs. MPU processes are more targeted and require fewer options. A TSMC SOC process for example would typically have 2 or more gate oxide thicknesses with options for 4 or more Vts while Intel’s MPU processes are single gate oxide and at 22nm were 3Vts. On the other hand Intel is now shipping 14nm MPUs while TSMC will not be shipping SOCs on 16nm until mid-next year (although Intel will likely not ship their SOC version of 14nm until next year either). Intel’s disclosure also shows a significant density advantage over TSMC at almost 20% for SRAM cell size.

Also read:Who Will Lead at 10nm?

The preceding numbers are all based on TSMC’s IEDM paper from last December. TSMC is also known to have an FF and FF+ process. The FF+ process shows significant improvements in performance over FF. Is this due to a shrink or what performance enhancement is used to achieve this? It will also be interesting to see how Samsung’s 14nm process compares once we have critical dimensions for them. I would be very interested to hear from any Semiwiki readers who can provide additional information on the TSMC or Samsung processes.

A critical metric for both processes will be cost. Intel has already disclosed that 14nm produces a significant cost reduction per transistor versus 22nm (at least for MPUs). Various industry observers have published articles projecting increased cost per transistor for foundries at both 20nm and 16nm/14nm. Our modeling suggests TSMC will achieve a cost reduction at 20nm and may achieve a small cost reduction at 16nm as well.

August 8, 2014August 22, 2024

Should we pay the price of Innovation?

Should we pay the price of Innovation?
by Eric Esteve on 08-08-2014 at 8:00 pm
Categories: Foundries, GlobalFoundries, TSMC

I agree that this question sounds stupid: nobody is forcing me to buy an innovative product, or even a gadget, if I don’t want to pay a high price, I just don’t buy the product. But it seems that some people don’t really think that way. The story is related to Qualcomm sales in China, and recently announced partnership with SMIC…

The Partnership (the fact)

From the joint Press Release: SAN DIEGO – July 03, 2014 – Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) and Qualcomm Incorporated (NASDAQ: QCOM), have announced that SMIC and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, are working together in connection with 28nm process technology and wafer manufacturing services in China to manufacture Qualcomm® Snapdragon™ processors. Qualcomm Technologies’ Snapdragon processors are purpose built for mobile devices. SMIC is one of China’s largest and most advanced semiconductor foundries, and Qualcomm Technologies is one of the world’s largest fabless semiconductor vendors and a world leader in 3G, 4G and next-generation wireless technologies. This collaboration will help accelerate SMIC’s 28nm process maturity and capacity, and will also make SMIC one of the first semiconductor foundries in China to offer production locally for some of Qualcomm Technologies’ latest Snapdragon processors on 28nm node, both PolySiON (PS) and high-K dielectrics metal gate (HKMG).

This PR sounds like both companies are enjoying a new partnership, maybe showing that one of the partners is getting higher benefit: “This collaboration will help accelerate SMIC’s 28nm process maturity and capacity, and will also make SMIC one of the first semiconductor foundries in China to offer production locally for some of Qualcomm Technologies’ latest Snapdragon processors on 28nm node…”. If you further analyze, “Qualcomm will help SMIC accelerate 28nm process maturity” sounds like the customer is devoting resources to help the supplier filling the technology gap with foundry competitors. If you prefer, this PR sounds like Qualcomm is paying an entry ticket to stay active and continue to sale Snapdragon on the Chinese market. Maybe this deal does not look any more like a win-win deal? The good question is to know why Qualcomm had to sign such a partnership?

I found a possible answer in this article from Junko Yoshida, Chief International Correspondent, EETimes “China’s SMIC-Qualcomm 28-nm Deal: Why Now? “, here is an extract:

Antitrust investigation in China
Since China launched an antitrust probe into Qualcomm late last year, speculation abounds that Chinese authorities are probing ways to coerce Qualcomm into collaborating with their electronics industry.
Qualcomm reportedly faces penalties that may exceed $1 billion. The National Development and Reform Commission (NDRC), China’s main planning body, raided Qualcomm’s Beijing and Shanghai offices last year.
The NDRC has used the anti-monopoly law to target technology companies for practices that could lead to what it calls “unreasonably” high prices. In February, the Chinese regulator said it suspects Qualcomm of overcharging and abusing its market position.

So the Chinese regulator (NDRC) considers that technology companies like Qualcomm are selling at “unreasonably” high prices. Let’s make a point: Qualcomm has invented and patented innovative modem techniques (CDMA and the like) for wireless communication, and these techniques have been selected by the telecommunication regulators in the USA (and other regions) to be at the hearth of the new standards. Qualcomm has a de facto monopoly, this is due to the international patent policy: every chip maker developing a modem has to pay a license and royalties to QCOM, and this gives a competitive advantage to Qualcomm when the company also develop modem IC. Qualcomm has been smart enough to also dominate the Application Processor market. The chip maker has just do a better job that TI, Nvidia, Marvell, Freescale… you name it. The equation is rather simple:

Innovation (Patent) + Investment (IC design) + Roadmap = Strong Leader position

As far as I am concerned, I don’t see any malfeasance in this strategy. We have seen in the past a high tech PC chip maker basing the company development, not only on a quasi-monopoly (leaving just enough room for a single competitor to survive, so the monopoly was not 100%), but also on anti-competitive practices (like paying back customers to make sure these will stay). Such a behavior has been sanctioned by the American law, and this was good decision. But the picture is completely different with Qualcomm. If you agree with the international patent policy, you must admit that a company cleaver enough to create innovation and turn it into a new technology and the related (IC) products should be in a position to harvest and get benefit from this innovation…

Let’s make it clear: I have no negative a-priori against China. But I may have a certain reluctance when I see politician (from any country) trying to squeeze innovation. At the end of the day, SMIC will get benefit from this partnership, detrimental to TSMC, Samsung or GloFo, and detrimental also to innovation.

Eric Esteve

Who will Manufacture Apple’s Next SoC?

Who will Manufacture Apple’s Next SoC?
by Daniel Nenni on 08-07-2014 at 8:00 pm
Categories: Foundries, Intel Foundry, TSMC

Just to review: The brain inside the current Apple iPhone 5s is the A7 SoC manufactured by Samsung using a 28nm process. The A6 (iPhone 5) and A5 (iPhone 4s) are based on Samsung 32nm. The rest of the Apple SoCs also used Samsung processes. I think we can all now agree that the coming Apple A8 SoC (iPhone 6) will use the TSMC 20nm process. In order to properly postulate which process the Apple A9 will use let me share with you my observations, opinions, and experience on the topic.

Also Read: Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?

In the beginning Apple started with Samsung as an ASIC customer where Apple did the preliminary design specifications and Samsung did the rest and delivered a completed chip. Over the course of the last ten years Apple evolved into one of the largest and most capable fabless semiconductor companies and now does everything required to get an SoC design into a foundry and the resulting chip into their products. In fact, Apple is now an “early access foundry customer” which means they are actively involved in early stage process development.

The important question is: Why did Apple leave Samsung for TSMC?

Apple is unique in that they release new mobile products in the fall of each year while competitors like Samsung release multiple products throughout the year. This ties the release of new foundry silicon to Apple’s new product releases since the volumes of wafers required are in the hundreds of thousands. Samsung’s delay from 32nm to 28nm was a big wake-up call for Apple. The iPhone 5 was supposed to contain 28nm silicon but clearly that did not happen which put Apple at a competitive disadvantage.

Since TSMC is the only foundry to release a new process node in 2014 (20nm) with the wafer capacity to satisfy Apple (Apple has asked its suppliers to build between 70 to 80 million iPhone 6 handsets by the end of the year), Apple moved to TSMC for the A8. Moving to TSMC also clearly demonstrates that Apple is truly an independent fabless semiconductor company and can choose any foundry moving forward. This will enable Apple to play Intel, Samsung, and TSMC against each other for better wafer pricing, absolutely.

Also read: What is the Latest in Mobile?

Apple’s first FinFET SoC is a very difficult situation. I know for a fact that Apple carefully considered Intel 14nm, Samsung 14nnm, and TSMC 16nm. The key criteria here is the iPhone 6s Fall of 2015 ship date. Which means the design must be taped-out by the end of Q3 2014 for production start in Q2 2015. Based on what I know today here are scenarios I would like to offer up for discussion:

Apple will NOT use Intel 14nm in 2015. Intel is still learning how to be a foundry and Apple is very demanding so there is a high element of relationship risk here. Apple is also VERY closely tied to ARM and Intel does not work with ARM on process development like TSMC and Samsung do. Intel 14nm also experienced big delays which increased the risk of missing the Apple Q2 2105 production start date.

Apple will NOT use TSMC 16nm in 2015. TSMC 16FF was on track to be in production 1H 2015 but the process was further optimized to be more competitive with Intel and Samsung. The new TSMC 16FF+ process will not be in production until 2H 2015 which will miss the Apple iPhone 6s launch.

Apple will NOT use Samsung 14nm in 2015. From what I understand today Samsung 14nm is still having silicon correlation problems. And as we have seen with Intel, yielding at 14nm is no small feat. The risk of missing critical wafer delivery dates here is very high.

Apple WILL use TSMC 20nm in 2015. It is my understanding that the Apple A8 will have a dual core CPU running at a maximum of 2GHZ and will not have an integrated modem. Thus the room for an improved A9 20nm SoC is pretty big, especially if Apple is concerned about 14nm FinFET production delays.

Bottom line: 14nm FinFET technology is still evolving, 20nm technology has room for improved power consumption and performance, and 10nm is years away. For Apple the low risk scenario is: 20nm SoCs in 2014 – 2015, 16nm SoCs in 2016 – 2017, and 10nm SoCs in 2018-2019. Sound reasonable?

Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?

Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?
by Daniel Nenni on 08-05-2014 at 10:00 pm
Categories: Foundries, Intel Foundry, TSMC

Speculation is running rampant after last month’s conference call where Dr. Morris Chang, who is often referred to as “The Chairman”, commented that at 16nm TSMC will have a smaller market share than a major competitor in 2015. TSMC will however regain the FinFET lead in 2016 and 2017. Of course the blogosphere went crazy on this which resulted in a hefty TSM stock price drop and some lengthy calls for me with Wall Street. Everybody, including myself, speculated that the major competitor referenced is Samsung. Is the Chairman using strategy to motivate the troops or does he really think TSMC will lose the first wave of FinFET designs? Now that the dust has settled let’s take another look at this hotly debated topic but first a little background:

SoC design increases in complexity as the architecture changes: 32 to 64 bit for example. Apple made this change with the iPhone 5s last year using the Samsung 28nm HKMG process node. Apple’s prior SoCs for the iPhone5 and iPhone 4s were also HKMG (Samsung 32nm) so this was more of an architectural design challenge versus a process design challenge. The other SoC vendors will not have 64 bit architectures in production until 2015 so this was not a trivial engineering feat.

SoC design also increases in complexity as more functions are integrated. The next big integration challenge will be putting a high speed radio (modem) on a 64 bit SoC using FinFETs. QCOM has both the leading mobile SoC and leading mobile modem and has already integrated them at 28nm. But I would not count Apple out since they have an experienced modem team working on it and they already have a 64-bit architecture in production.

SoC design at leading edge nodes is extremely challenging as we can see by the delays in 20nm and 14nm. TSMC 20nm was delayed six months and Intel 14nm is more than a year late. TSMC 16nm and Samsung 14nm are not in production yet but will no doubt be later than we all expected. Delays happen when you challenge the laws of physics as we do most every day, absolutely.

Now let’s go back to the conference call and look at a key piece of information in the Q&A that most people glossed over:

Elizabeth Sun: “Randy’s question is with respect to Chairman’s comment on 2015’s market share is lower than a major competitor in 2015. So Randy’s asking why will it be lower and what is the impact to TSMC if we have a lower market share. And what gives us the confidence that we will regain the market share in following year?”

Morris Chang – TSMC – Chairman: “Oh, okay. Well, we need to go back to history a little bit. 32 — 28-nanometer followed 32 and that particular major competitor that I referred to, chose 32 and skipped 28. And then of course we came to 20 and 16, 16 for us, 14 for him. And we chose to do both. Actually we chose to do 20 first and 16 about a year or so later, but it was a pretty quick succession. And this major competitor skipped 20 and went on to 16.”

As I mentioned, Samsung did both 32nm and 28nm. Intel did 32nm and skipped 28nm so it seems the Chairman was referring to Intel as the competitor that will have a larger 14/16nm foundry market share in 2015, not Samsung. Comments?

July 25, 2014June 14, 2019

Temperature – The Fourth Aspect to Look at in SoC Design

Temperature – The Fourth Aspect to Look at in SoC Design
by Pawan Fangaria on 07-25-2014 at 2:00 pm
Categories: EDA, Siemens EDA, TSMC

In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip and density of the design, power has become critical to the design. And excessive power consumption has given rise to a fourth parameter, temperature to consider at the beginning of the design; it’s no longer uniform across the die. Further, a thinner die is losing its heat spreading capability. Considering the kind of high heat generation inside the chips now a day, temperature has become a critical aspect to look at, not only its generation due to power consumption, but also separately by taking into account the planning of temperature distribution and diffusion, thermal properties of materials, and collaborating between mechanical and electrical design flow. In case of stacked dies in 3DICs, it’s essential that proper mechanisms are planned to get the heat out of the stack. The placement of TSVs (Through Silicon Vias) near high power regions can significantly improve the overall thermal performance of a 3DIC.

Mentor Graphicswith its experience through the use of its tools in TSMC’s CoWoS Reference Flow for design, verification, thermal and test solutions, and a study with experts have proposed key guidelines for thermal management which can be followed through a design flow from start of the design.

It’s important to consider the chip-package co-design, starting with the package construction (which may be mounted on a PCB) in the thermal model such that the effect of heat spreading in the board and into any heat sink (if planned) are accounted for in predicting the package temperature distribution. It requires a complete CFD (Computational Fluid Dynamics) simulation to study and predict the thermal interaction of the package with its environment. In the beginning of a design, a 3D thermal conduction model for the whole package as per the number of dies and budgeted power for each die can be planned very effectively and temperature data back-annotated to the IC design flow.

Explore the package design space with different package materials, die arrangements, package design, size and options and so on. The temperature influencing parameters such as TSV layout, interposer shape, size and material, glue layers, cooling solutions, stack design etc. can be studied at this stage.

The temperature-dependent thermal properties must be included. Mentor’s FloTHERM has a material library which includes all kinds of materials with their thermal properties such as temperature-dependent thermal conductivity, specific heat capacity and material density to accurately predict hot spots on a die.

The die surface treatment should be refined by including a 3D representation of the active layers (consisting of metal wires separated by dielectric materials) of the die approximated to an isotropic block within the thickness of one mesh cell in the package-level model.

It’s interesting to note that by this time the bulk top-level planning is done to estimate the average die temperature and temperature variation for each die. This information of temperature can be back-annotated before floorplanning that can help the IC design team to effectively partition and floorplan the design appropriately at the start of the design process.

Now it’s time to refine the package further with input from the IC design team; the power map after floorplanning can be imported into the thermal model of the package. FloTHERM has a Die SmartPart that allows power to be read in as CSV file automatically and the thermal simulation model can quickly indicate where TSVs can be introduced to improve the thermal performance, or where design changes are needed such as to ensure a few functional blocks to operate at similar temperatures to eliminate timing issues. The functional blocks can be moved keeping their relative positions intact and optimizing the white spaces for insertion of TSVs. By using FloTHERM, an assessment of the impact of TSVs on the die hot spots can be easily done. Knowing the TSV size and pitch, which scale with die thickness, blocks of higher through-plane thermal conductivity can be superimposed over the die thickness in the white spaces in FloTHERM, to locally override the properties of silicon.

With the progress of the floorplanning and detailed thermal interaction between die, the power map for the die becomes much more detailed, thus making the IC design flow temperature aware. The thermal map created from power map (generated by power analysis tools) can be used for thermal design and checking against thermal constraints.

The FloTHERM is embedded into Mentor’s Calibre suite which enabled the creation of TSMC reference flow for thermal analysis based on FloTHERM and Calibre DESIGNrev and RVE, an industry standard physical verification result viewing environment. The automatic gridding (using localized grid in critical areas) built into this system enables very efficient, fast and accurate thermal simulation on dies and interposers of 3DIC.

The thermal results can be displayed as histogram in Calibre RVE and the hot spots highlighted in Calibre DESIGNrev. In case of transient analysis, EZwave can be used to display temperature vs. time graph.

A 3DIC thermal model can be created to allow the 3DIC package to be imported into a larger system for further thermal simulation at the system level. A detailed study of the chip-package thermal co-design process can be found in a whitepaper at the Mentor website.