TSMC – Page 40 – SemiWiki

August 7, 2014

Who will Manufacture Apple’s Next SoC?

Who will Manufacture Apple’s Next SoC?
by Daniel Nenni on 08-07-2014 at 8:00 pm
Categories: Foundries, Intel Foundry, TSMC

Just to review: The brain inside the current Apple iPhone 5s is the A7 SoC manufactured by Samsung using a 28nm process. The A6 (iPhone 5) and A5 (iPhone 4s) are based on Samsung 32nm. The rest of the Apple SoCs also used Samsung processes. I think we can all now agree that the coming Apple A8 SoC (iPhone 6) will use the TSMC 20nm process. In order to properly postulate which process the Apple A9 will use let me share with you my observations, opinions, and experience on the topic.

Also Read: Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?

In the beginning Apple started with Samsung as an ASIC customer where Apple did the preliminary design specifications and Samsung did the rest and delivered a completed chip. Over the course of the last ten years Apple evolved into one of the largest and most capable fabless semiconductor companies and now does everything required to get an SoC design into a foundry and the resulting chip into their products. In fact, Apple is now an “early access foundry customer” which means they are actively involved in early stage process development.

The important question is: Why did Apple leave Samsung for TSMC?

Apple is unique in that they release new mobile products in the fall of each year while competitors like Samsung release multiple products throughout the year. This ties the release of new foundry silicon to Apple’s new product releases since the volumes of wafers required are in the hundreds of thousands. Samsung’s delay from 32nm to 28nm was a big wake-up call for Apple. The iPhone 5 was supposed to contain 28nm silicon but clearly that did not happen which put Apple at a competitive disadvantage.

Since TSMC is the only foundry to release a new process node in 2014 (20nm) with the wafer capacity to satisfy Apple (Apple has asked its suppliers to build between 70 to 80 million iPhone 6 handsets by the end of the year), Apple moved to TSMC for the A8. Moving to TSMC also clearly demonstrates that Apple is truly an independent fabless semiconductor company and can choose any foundry moving forward. This will enable Apple to play Intel, Samsung, and TSMC against each other for better wafer pricing, absolutely.

Also read: What is the Latest in Mobile?

Apple’s first FinFET SoC is a very difficult situation. I know for a fact that Apple carefully considered Intel 14nm, Samsung 14nnm, and TSMC 16nm. The key criteria here is the iPhone 6s Fall of 2015 ship date. Which means the design must be taped-out by the end of Q3 2014 for production start in Q2 2015. Based on what I know today here are scenarios I would like to offer up for discussion:

Apple will NOT use Intel 14nm in 2015. Intel is still learning how to be a foundry and Apple is very demanding so there is a high element of relationship risk here. Apple is also VERY closely tied to ARM and Intel does not work with ARM on process development like TSMC and Samsung do. Intel 14nm also experienced big delays which increased the risk of missing the Apple Q2 2105 production start date.

Apple will NOT use TSMC 16nm in 2015. TSMC 16FF was on track to be in production 1H 2015 but the process was further optimized to be more competitive with Intel and Samsung. The new TSMC 16FF+ process will not be in production until 2H 2015 which will miss the Apple iPhone 6s launch.

Apple will NOT use Samsung 14nm in 2015. From what I understand today Samsung 14nm is still having silicon correlation problems. And as we have seen with Intel, yielding at 14nm is no small feat. The risk of missing critical wafer delivery dates here is very high.

Apple WILL use TSMC 20nm in 2015. It is my understanding that the Apple A8 will have a dual core CPU running at a maximum of 2GHZ and will not have an integrated modem. Thus the room for an improved A9 20nm SoC is pretty big, especially if Apple is concerned about 14nm FinFET production delays.

Bottom line: 14nm FinFET technology is still evolving, 20nm technology has room for improved power consumption and performance, and 10nm is years away. For Apple the low risk scenario is: 20nm SoCs in 2014 – 2015, 16nm SoCs in 2016 – 2017, and 10nm SoCs in 2018-2019. Sound reasonable?

Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?

Will Intel Have a Bigger FinFET Market Share Than TSMC in 2015?
by Daniel Nenni on 08-05-2014 at 10:00 pm
Categories: Foundries, Intel Foundry, TSMC

Speculation is running rampant after last month’s conference call where Dr. Morris Chang, who is often referred to as “The Chairman”, commented that at 16nm TSMC will have a smaller market share than a major competitor in 2015. TSMC will however regain the FinFET lead in 2016 and 2017. Of course the blogosphere went crazy on this which resulted in a hefty TSM stock price drop and some lengthy calls for me with Wall Street. Everybody, including myself, speculated that the major competitor referenced is Samsung. Is the Chairman using strategy to motivate the troops or does he really think TSMC will lose the first wave of FinFET designs? Now that the dust has settled let’s take another look at this hotly debated topic but first a little background:

SoC design increases in complexity as the architecture changes: 32 to 64 bit for example. Apple made this change with the iPhone 5s last year using the Samsung 28nm HKMG process node. Apple’s prior SoCs for the iPhone5 and iPhone 4s were also HKMG (Samsung 32nm) so this was more of an architectural design challenge versus a process design challenge. The other SoC vendors will not have 64 bit architectures in production until 2015 so this was not a trivial engineering feat.

SoC design also increases in complexity as more functions are integrated. The next big integration challenge will be putting a high speed radio (modem) on a 64 bit SoC using FinFETs. QCOM has both the leading mobile SoC and leading mobile modem and has already integrated them at 28nm. But I would not count Apple out since they have an experienced modem team working on it and they already have a 64-bit architecture in production.

SoC design at leading edge nodes is extremely challenging as we can see by the delays in 20nm and 14nm. TSMC 20nm was delayed six months and Intel 14nm is more than a year late. TSMC 16nm and Samsung 14nm are not in production yet but will no doubt be later than we all expected. Delays happen when you challenge the laws of physics as we do most every day, absolutely.

Now let’s go back to the conference call and look at a key piece of information in the Q&A that most people glossed over:

Elizabeth Sun: “Randy’s question is with respect to Chairman’s comment on 2015’s market share is lower than a major competitor in 2015. So Randy’s asking why will it be lower and what is the impact to TSMC if we have a lower market share. And what gives us the confidence that we will regain the market share in following year?”

Morris Chang – TSMC – Chairman: “Oh, okay. Well, we need to go back to history a little bit. 32 — 28-nanometer followed 32 and that particular major competitor that I referred to, chose 32 and skipped 28. And then of course we came to 20 and 16, 16 for us, 14 for him. And we chose to do both. Actually we chose to do 20 first and 16 about a year or so later, but it was a pretty quick succession. And this major competitor skipped 20 and went on to 16.”

As I mentioned, Samsung did both 32nm and 28nm. Intel did 32nm and skipped 28nm so it seems the Chairman was referring to Intel as the competitor that will have a larger 14/16nm foundry market share in 2015, not Samsung. Comments?

July 25, 2014June 14, 2019

Temperature – The Fourth Aspect to Look at in SoC Design

Temperature – The Fourth Aspect to Look at in SoC Design
by Pawan Fangaria on 07-25-2014 at 2:00 pm
Categories: EDA, Siemens EDA, TSMC

In my career in semiconductor industry, I can recall, in the beginning there was emphasis on design completion with automation as fast as possible. The primary considerations were area and speed of completion of a semiconductor design. Today, with unprecedented increase in multiple functions on the same chip and density of the design, power has become critical to the design. And excessive power consumption has given rise to a fourth parameter, temperature to consider at the beginning of the design; it’s no longer uniform across the die. Further, a thinner die is losing its heat spreading capability. Considering the kind of high heat generation inside the chips now a day, temperature has become a critical aspect to look at, not only its generation due to power consumption, but also separately by taking into account the planning of temperature distribution and diffusion, thermal properties of materials, and collaborating between mechanical and electrical design flow. In case of stacked dies in 3DICs, it’s essential that proper mechanisms are planned to get the heat out of the stack. The placement of TSVs (Through Silicon Vias) near high power regions can significantly improve the overall thermal performance of a 3DIC.

Mentor Graphicswith its experience through the use of its tools in TSMC’s CoWoS Reference Flow for design, verification, thermal and test solutions, and a study with experts have proposed key guidelines for thermal management which can be followed through a design flow from start of the design.

It’s important to consider the chip-package co-design, starting with the package construction (which may be mounted on a PCB) in the thermal model such that the effect of heat spreading in the board and into any heat sink (if planned) are accounted for in predicting the package temperature distribution. It requires a complete CFD (Computational Fluid Dynamics) simulation to study and predict the thermal interaction of the package with its environment. In the beginning of a design, a 3D thermal conduction model for the whole package as per the number of dies and budgeted power for each die can be planned very effectively and temperature data back-annotated to the IC design flow.

Explore the package design space with different package materials, die arrangements, package design, size and options and so on. The temperature influencing parameters such as TSV layout, interposer shape, size and material, glue layers, cooling solutions, stack design etc. can be studied at this stage.

The temperature-dependent thermal properties must be included. Mentor’s FloTHERM has a material library which includes all kinds of materials with their thermal properties such as temperature-dependent thermal conductivity, specific heat capacity and material density to accurately predict hot spots on a die.

The die surface treatment should be refined by including a 3D representation of the active layers (consisting of metal wires separated by dielectric materials) of the die approximated to an isotropic block within the thickness of one mesh cell in the package-level model.

It’s interesting to note that by this time the bulk top-level planning is done to estimate the average die temperature and temperature variation for each die. This information of temperature can be back-annotated before floorplanning that can help the IC design team to effectively partition and floorplan the design appropriately at the start of the design process.

Now it’s time to refine the package further with input from the IC design team; the power map after floorplanning can be imported into the thermal model of the package. FloTHERM has a Die SmartPart that allows power to be read in as CSV file automatically and the thermal simulation model can quickly indicate where TSVs can be introduced to improve the thermal performance, or where design changes are needed such as to ensure a few functional blocks to operate at similar temperatures to eliminate timing issues. The functional blocks can be moved keeping their relative positions intact and optimizing the white spaces for insertion of TSVs. By using FloTHERM, an assessment of the impact of TSVs on the die hot spots can be easily done. Knowing the TSV size and pitch, which scale with die thickness, blocks of higher through-plane thermal conductivity can be superimposed over the die thickness in the white spaces in FloTHERM, to locally override the properties of silicon.

With the progress of the floorplanning and detailed thermal interaction between die, the power map for the die becomes much more detailed, thus making the IC design flow temperature aware. The thermal map created from power map (generated by power analysis tools) can be used for thermal design and checking against thermal constraints.

The FloTHERM is embedded into Mentor’s Calibre suite which enabled the creation of TSMC reference flow for thermal analysis based on FloTHERM and Calibre DESIGNrev and RVE, an industry standard physical verification result viewing environment. The automatic gridding (using localized grid in critical areas) built into this system enables very efficient, fast and accurate thermal simulation on dies and interposers of 3DIC.

The thermal results can be displayed as histogram in Calibre RVE and the hot spots highlighted in Calibre DESIGNrev. In case of transient analysis, EZwave can be used to display temperature vs. time graph.

A 3DIC thermal model can be created to allow the 3DIC package to be imported into a larger system for further thermal simulation at the system level. A detailed study of the chip-package thermal co-design process can be found in a whitepaper at the Mentor website.

The Leading Edge Foundry Landscape

The Leading Edge Foundry Landscape
by Scotten Jones on 07-22-2014 at 7:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

There have been a lot of interesting announcements and presentations lately from the leading edge foundries. Looking at all of this information, a pretty interesting picture begins to emerge.

TSMC
TSMC is far and away the world’s largest foundry. In their 2014-Q2 conference call TSMC outlined their expectations for the balance of 2014 out through 2015.

At 28nm TSMC has LP (low power), HP (high performance), HPL (low power with HKMG) and HPM (high performance mobile). All four processes are bulk planar process with gate-last HKMG except LP that is polysilicon and SiON. At 28nm TSMC had the dominant market share, Samsung captured the Apple processor business and TSMC pretty much had everything else.

TSMC is now ramping 20nm (bulk planar process), they are expecting 20nm to be 10% of revenue in Q3 and 20% in Q4. Furthermore TSMC expects 20nm to be >20% of revenue for 2015. TSMC expects to dominate 20nm and discussed a major competitor skipping 20nm (without naming names, but we will get to who it is later). On TSMC’s web site they report that 20nm gives a 1.9x density improvement over 28nm.

At 16nm TSMC will not be ramping until Q3 of 2015 (FinFET on bulk process). Due to competitors having 14nm in the market in the first half of 2015 TSMC expects to initially have no share and lower share for 2015 in total. Longer term, TSMC expects to catch up and they expect that the combined 20nm/16nm market share will be higher than anyone else throughout 2014, 2015 and 2016. As a side note the development and design cycles are long enough that TSMC has a lot of visibility on who their customers will be all the way through 16nm. The 16nm process is a 16nm FinFET on bulk front end with the 20nm backend. I haven’t seen any statements from TSMC on overall density improvements but I have heard approximately 1.05x

For 10nm TSMC is forecasting 2.2x density improvement (FinFET on bulk). They declined to give any specific guidance on timing.

Also read: The Great 28nm Debacle!

Samsung
Samsung is the world’s third largest foundry. Dan Nenni recently published an interesting article on Samsung on Semiwiki and that article includes a link to a Samsung foundry presentation. The presentation discusses 28nm and 14nm but not 20nm so presumably Samsung is the competitor TSMC is referring to as “skipping” 20nm. This is particularly interesting because I had seen reports not that long ago that Samsung was going to be making at least some 20nm processors for Apple. I can only guess, but perhaps Apple went 100% with TSMC at 20nm and Samsung abandoned 20nm due to lack of customers.

At 28nm Samsung has 28LPS (cost effective), 28LPP (low power RF enabled), 28LPH (high performance) all planar on bulk and 28FD-SOI high performance “20nm performance at 28nm cost”. Given that Samsung is skipping 20nm it looks very likely that Samsung has licensed 28 FD-SOI technology to fill the 20nm gap. Samsung is gate-first for HKMG.

At 14nm Samsung has 14LPE (FinFET on bulk) as their fast time to market product and 14LPP (FinFET on bulk) as their second generation performance boosted product. 14LPE is qualified now and 14LPP is due in Q1-2015. Dan Nenni has suggested that Apple will go sole source with TSMC at 20nm and then jump back to Samsung at 14nm. Samsung’s 14nm should ramp late 2104 and early 2015 and represent the 14nm/16nm market share loss TSMC mentioned.

Samsung also reports that 14nm will have 0.55x the area of 28nm (for both LPE and LPP), that is a 1.82x density improvement. If TSMC sees a 1.9x improvement for 20nm over 28nm and another 1.05x at 16nm over 20nm, they would see a 2.00x density improvement for 16nm versus 28nm (please note TSMC’s 16nm process is really what everyone else is calling 14nm, the number 14 is apparently unfavorable in Taiwan). Assuming both companies have similar density at 28nm then TSMC could potentially have a density advantage at 16nm.

The iPhone6 will have TSMC 20nm, Absolutely!

The iPhone6 will have TSMC 20nm, Absolutely!
by Daniel Nenni on 07-13-2014 at 11:00 am
Categories: Foundries, TSMC

TSMC 20nm is one of the most talked about nodes on SemiWiki with lots of speculation and debate surrounding it. It’s interesting to look back at what we thought would happen to see if it actually did happen so let’s do that now. According to Google there are 411 articles referencing 20nm on SemiWiki, let’s visit a couple of the more interesting ones written by me (of course). This article is really for my beautiful wife and four children who rarely think I’m right so please don’t point out where I was wrong:

3D Transistors @ TSMC 20nm!
by Daniel Nenni
Published on 11-06-2011
Ever since the TSMC OIP Forum where Dr. Shang-Yi Chiang openly asked customers, “When do you want 3D Transistors (FinFETS)?” I have heard quite a few debates on the topic inside the top fabless semiconductor companies. The bottom line, in my expert opinion, is that TSMC will add FinFETS to the N20 (20nm) process node in parallel with planar transistors and here are the reasons why:

Dragon Boats and TSMC 20nm Update!
by Daniel Nenni
Published on 07-01-2012
Even more exciting, TSMC has 20nm up on the TSMC website now! Exciting for me at least! This is really cool stuff and it is right around the corner. I also like the new TSMC website and banner ads. It really does show a much more progressive communication style for a foundry…… Expect 20nm risk production to start in Q4 2013, two years to the quarter after 28nm.

Apple Will NOT Manufacture SoCs at Intel
by Daniel Nenni
Published on 12-09-2012
My bet is: moving forward Apple will use Samsung for 28nm (iPhone 5s) and TSMC for 20nm (iPhone 6). Intel certainly has a shot at 14nm and 10nm but never ever count out TSMC. If you want to bet a lunch on Apple manufacturing at Samsung or Intel for 20nm post it in the comment section. I will cover all lunch bets against TSMC.

TSMC 28nm and 20nm Update Q4 2012
By Daniel Nenni
Published on 12-16-2012
20nm will be a much more interesting node in regards to competition however. After learning the gate-first lesson, IBM is following TSMC with a gate-last HKMG implementation at 20nm. Unfortunately the added difficulty of 20nm double patterning and lithography challenges, which have yet to be solved at a production level, is causing delays. The fabless semiconductor ecosystem is working around the clock on this and I honestly expect a hockey stick 20nm production curve once this has been solved.

TSMC Apple Rumors Debunked!
by Daniel Nenni
Published on 01-11-2013
The first rumor is that the next Apple A7 processor (28nm) will be made by TSMC. That rumor is FALSE! As I previously blogged, the Apple iPhone to be released this year (iPhone 5s) will be Samsung 28nm. The iPhone to be released next year (iPhone 6) will be TSMC 20nm. A company the size of Apple cannot switch foundries on a moment’s notice. The volumes are too high and the technology issues are too complex. I have no doubt Apple discussed 28nm with TSMC but since no other foundries had 28nm available there was no way TSMC could handle the wafer demands of Apple and the rest of the fabless companies. Apple also gets preferred pricing so why would TSMC give up higher margin 28nm business AND alienate their customer base? Not going to happen….

Where will Apple Manufacture the next iPhone Brain?
by Daniel Nenni
Published on 07-17-2013
There still seems to be a lot of confusion here so let me set the record straight. In regards to the Apple Ax SoC, the Apple iPhone 5s will have Samsung 28nm Silicon. Samsung 28nm is still ramping but Samsung can make enough wafers and eat the yield issues no problem. The Apple iPhone 6 in 2014 will have TSMC 20nm as I reported previously.

Also read: Intel 14nm Delayed Yet Again?

The Great 28nm Debacle!

The Great 28nm Debacle!
by Daniel Nenni on 07-06-2014 at 9:00 am
Categories: Foundries, TSMC

40nm was a big node while I was Director of Foundries at the IP company Virage Logic which was later acquired by Synopsys. 40nm was big because the top fabless companies multi-sourced designs from one foundry to another with relative ease to get the best wafer prices. It was also the node where some of the big IDMs went fab-lite moving their leading edge IP and designs to the pure-play foundries.

I totally get the need for multi-sourcing. In my personal life I multisource my technology needs so I’m not beholden to any one company. I use FireFox for browsing, Yahoo for news, Google for search and maps, iPhones and iPads, Microsoft based laptops, it seems like human nature 2.0. In business however it’s a double edged sword, absolutely.

Since TSMC was first to 40nm, they did most of the heavy lifting only to see mass production moved to UMC, Chartered, and SMIC. I remember feeling bad for the TSMC wafer sales team doing all the work and not getting the appropriate rewards. I also remember wondering about the TSMC IP embedded in the GDS II design data (design rules etc…) moving about the world. Some fabless companies did their own design rules as a superset of the foundries to make sure designs were portable. Others just handed over TSMC GDS II and said, “Make this please.”

28nm changed things of course when TSMC was the only foundry to yield so it was the first and last full node for single source manufacturing we will ever see, my opinion. The TSMC 28nm fabs have been pretty much full since the first wafers shipped in Q4 2011. 28nm wafers were even on allocation at times which made the entire fabless semiconductor ecosystem uneasy. It also hit the fabless margins hard since TSMC did not have any pricing pressure. Considering what happened at 40nm the record high 28nm margins TSMC realized were well earned.

I remember the fabless quarterly conference calls in 2012 where the CEOs blamed 28nm wafer shortages for earnings misses which implied TSMC was not doing their job. It would have been nice if the CEOs were a bit more humble and admitted that TSMC did in fact ship the wafers under contract and it was their reliance on multi-sourcing that did them in this time. TSMC could have certainly built out enough 28nm capacity to prevent shortages had they been asked, right?

The 28nm landscape is changing again now that UMC, SMIC, GF, and Samsung are yielding enough to make a profit. Not the same profit as TSMC of course since they have the best yield and the fabs have been paid for many times over the last 2.5 years. At the same time TSMC is the only fab to ramp 20nm with production parts from Xilinx (FPGA), QCOM (modem), and Apple (SoC) hitting the market this year so the margins will keep pouring in.

“Handel Jones is WRONG about 20nm by one year. According to JK Wang, Vice President of Operations for 300mm fabs, TSMC will ship 300,000 20nm wafers in 2014 and 1,000,000 20nm wafers in 2015.“

The TSMC Q2 2014 conference call on July 17[SUP]th[/SUP] will reveal just how much 20nm revenue will be recognized so let’s talk after that.

June 23, 2014

Cliff Hou’s DAC Keynote

Cliff Hou’s DAC Keynote
by Paul McLellan on 06-23-2014 at 10:21 am
Categories: Foundries, TSMC

Cliff Hou had two major appearances at DAC this year. He gave the opening day keynote…and he wrote the forward to Dan and my bookFabless: the Transformation of the Semiconductor Industry which about 1500 lucky people got a copy of courtesy of several companies, most notably eSilicon who sponsored the Tuesday evening post-conference party where we signed several hundred copies. You can still get a copy if you missed out, just click on the book cover on the top left hand side of the front page of SemiWiki.

Cliff’s keynote was about the future challenges of getting to 10nm and beyond. 14/16nm (they are basically the same despite the different numbers) are pretty much a done deal. Not yet in volume production but on track to get there later this year.

Cliff started by talking about mobile which is what drives semiconductor leading edge processes. Design innovation drives process innovation which enables more design innovation. As a result we have product innovation. It seems like we have always had smartphones but in fact the iPhone only came along 7 years ago. Up until then we had dumbphones although some marketing guy at Nokia cleverly called them feature phones to make them seem…almost smart.

Of course every process generation things get harder. Double patterning, FinFETs, multiple-patterning and so on. The big challenge is that as we approach 10nm, everything becomes more costly and so the economic driver that has been behind the semiconductor industry for the last few decades is weakening. It seems clear that the technical challenges can be overcome but at what cost?

There are two different sets of challenges getting to each new process node: the process issues, mostly around lithography, and the ecosystem issues.

lithography: continue to scale 193nm immersion
device: continue to deliver 25-30% speed gain at the same or reduced power
interconnect: address escalating parasitics
production: ramp volume in time to meet end-customer demand
shortened development runway to meet product windows

Design and technology co-optimization used to be fairly straighforward. The best local optimum was also the best overall optimum: shortest wire length the best, best gate-density the best area scaling, best technology also best cost. But these rules don’t hold any more. Everything has to be co-optimized from process, EDA tools and IP. If one of these is not up in time then the designs cannot be completed and the fab will not be filled as soon as capacity is available. And given the cost of a fab at $5-8B then a fab that is not full costs a huge amount in depreciation.

The time to get to market is speeding up too. First test chip, first PDK, first shuttle, volume production, the big milestones on a new node are getting compressed. At 10nm, Cliff reckons they will be roughly half the time they had at 28nm. The cost of bringing the process up and building the fabs to run it makes it imperative to start recovering the cost as soon as possible.

Bottom line: this all requires much closer collaboration between all the partners to make everything work in a timely manner. This is the key to unlock 10nm and beyond and turn the vision into reality.

TSMC (TSM) is Having Another SoC Year!

TSMC (TSM) is Having Another SoC Year!
by Daniel Nenni on 06-18-2014 at 9:00 am
Categories: Foundries, TSMC

TSMC’s stock has more than doubled in the last five years. Coincidentally that is when I started blogging about TSMC. QCOM stock has experienced a similar doubling during this time as have other TSMC customers. The question is: What is next for TSMC? As I have mentioned before, you would be better off taking stock tips from your dog but this is what I see for this year and next for TSM.

Apple will become one of TSMC’s largest customers in 2014. This is simply amazing to me as I grew up with Apple as a computer hobbyist. Apple started selling mother boards before selling complete computer systems. In fact, I was at the UC Berkeley Campus when Steve Jobs entered wearing a backpack with a Macintosh computer inside ushering in a new era of personal computing. And now Apple is one of the largest fabless semiconductor companies? It boggles the mind!

The quarterly wafer ramping numbers I have read for Apple are $0 to $700M per quarter this year starting in Q2 2014 and up from there depending on the success of the iPhone6 and iPads to be announced later this year. As I have mentioned before, I predict that the iPhone6 will break revenue records and it is filled with TSMC silicon, absolutely. Given that TSMC will ship 300,000 20nm wafers in 2014, Apple will probably consume most of them. The other SoC vendors are still scrambling to get 64-bit 20nm SoCs taped-out. Apple really disrupted the SoC business with their 64-bit A7!

In 2015 Apple business could result in an additional $1B per quarter for TSM. Based on what I heard at #51DAC the TSMC/Apple relationship will continue into the FinFET era. One interesting note; I saw quite a few Apple badges at #51DAC, which was not the case at #50DAC. Those Apple engineers are becoming more plentiful and less stealthy it seems.

QCOM however is TSMC’s largest customer. QCOM consumed a record number of wafers last year, roughly a 50% YoY increase. FinFET is the big question, will they go TSMC or Samsung? I can tell you for a fact that QCOM will not use Intel Foundry, nor will any other SoC vendor that has a choice. It may have something to do with Intel flooding the market with free 22nm SoCs? Let’s see how many of those 40 million “contra revenue” parts actually make it into consumer’s hands. Ironically Intel will be using TSMC 28nm for their new Sofia SoC but I would not expect any volumes there either unless Intel goes contra revenue again.

The latest word from #51DAC is that QCOM will straddle TSMC and Samsung for FinFET wafers to get better margins. TSMC’s margins are at an all-time high (36%) and QCOM’s are at an all-time low (16%) so you do the math. A Samsung/QCOM foundry relationship seemed like a natural fit since Samsung is one of QCOM’s largest customers but with the launch of the Samsung Exynos SoC in 2010 the two companies are now frenemies. As they say, keep your friends close but your enemies closer. That is from the book “GodFather II” by the way. Michael Corleone said, “My father taught me many things here — he taught me in this room. He taught me — keep your friends close but your enemies closer.”

The other SoC vendor that I track is MediaTek. They are literally down the street from TSMC and UMC so I see them during my Taiwan travels. MediaTek is an interesting company that has done extremely well in the low end SoC business. I view MediaTek, TSMC, and UMC as brothers so I highly doubt they would use GlobalFoundries or Samsung but it is certainly possible. In this business margins are everything.

June 12, 2014

GDS II Online for TSMC

GDS II Online for TSMC
by Paul McLellan on 06-12-2014 at 4:00 pm
Categories: eSilicon, Foundries, Semiconductor Services, TSMC

I just watched an interesting video of a demonstration at DAC of the eSilicon GDS II online quote for TSMC. Actually, it wasn’t so much as a demonstration as an interactive use of the quote tool using data supplied by a member of the audience.

The quote system works for TSMC processes from 28nm up to 350nm. The design the audience member wants quoted is a transceiver in TSMC’s 180nm process, mixed signal variant, with 6 layers of metal. The die size and package are specified (although for some reason that part of the video has been edited out).

A press of a button and the quote is created. It is very detailed.

package design $14,270
manufacturing services (test harness, probecards etc) $155,817
ESD qualification $9.500
test development $50,200
then there are lots of optional services that are priced such as burn-in, process corner analysis
lot buy pricing for 25,12 and 6 wafer lots at $73,866, $38,571 and $19,286 respectively, expected to yield 86,662 die, 41,598 die and 20,799 die
respin pricing (for a metal only change using some wafers held back at contact)

Finally the die price which is $2.35 assuming 90% wafer-sort yield (if the yield is 95% then $2.29 and at 85% $2.43).

The entire quote takes a little less than 10 minutes. And it is a quote not an estimate. Provided you don’t change anything (like the die size) then eSilicon stands behind the quote and will deliver all the services at the prices in the quote. Of course under the hood they have a TSMC price model built into the system, but that is transparent to you the customer. eSilicon takes care of all the negotiation with TSMC, the logistics of manufacturing, packaging, test, delivery and the various optional services, if any, that you have requested. Until recently, pricing a design was something that took a couple of weeks, and was anything but transparent. Now eSilicon, with the help of TSMC of course, have made something that used to take several weeks be just a few minutes.

Of course if something does change, for instance the die comes in larger or smaller than forecast when the quote was first done, then it only takes 10 minutes to generate a new quote and eSilicon will stand behind those revised prices. It is a big change from how I remember we used to do quotes when I was in the ASIC business in the 1980s.

Unfortunately eSilicon don’t have all the permissions they need to post the video so I can’t give you a link to it. I guess you just had to be there.

TSMC vs Intel vs Samsung FinFETs

TSMC vs Intel vs Samsung FinFETs
by Daniel Nenni on 06-08-2014 at 10:50 am
Categories: Foundries, TSMC

By definition the pure-play foundry business model separates the design and manufacturing of a semiconductor device. TSMC was the first dedicated (pure-play) foundry which enabled the incredible fabless semiconductor ecosystem we have today. If not for the fabless business model we would not have the supercomputer class mobile devices in our pockets. We, as integral parts of the fabless semiconductor ecosystem, have changed the world, absolutely.

So the question is: As an executive for a fabless semiconductor company, why would you even consider turning back the clock and renting fab space from an IDM (a company that both designs and manufactures semiconductor devices)?

As a student of history I have always felt that it is critical to understand how you got to where you are today in order to predict where you will be tomorrow. As a 30 year veteran of Silicon Valley I have seen many companies succeed but I have also seen many more fail due to one fundamental truth, they failed at the future. In writing “Fabless: The Transformation of the Semiconductor Industry” Paul McLellan and I both agree that the key to the fabless business model is competition. Unfortunately, at 28nm there was no real foundry competition and that has opened the foundry business doors to IDMs once again.

You can’t fault TSMC. They executed at 28nm and were rewarded with a dominant market position. Had GlobalFoundries been able to provide a competitive 28nm offering I would not be writing this blog. Trust me on this: fabless semiconductor companies would NOT even consider doing business with an IDM foundry if they had two or more leading edge pure-play foundry options.

Intel thinks they are clever by getting into the foundry business. Unfortunately Intel is being used as a pawn in a very high stakes game of foundry chess. I also believe this to be true in the SoC business but that is another blog. Samsung on the other hand is a chess grandmaster which puts Intel between a serious rock (Samsung) and a very hard place (TSMC). Take a close look at Samsung’s latest announcements:

Samsung ♥ GLOBALFOUNDRIES

Samsung Endorses FD-SOI!

Both are excellent moves in becoming an integral part of the fabless semiconductor ecosystem. Samsung is also the only foundry to show working 14nm Silicon at the Design Automation Conference last week. My sources tell me that Samsung 14nm is 3-6 months ahead of TSMC’s 16FF+. My sources also tell me that TSMC 16nm FF+ is today the most competitive FinFET offering, meaning power, performance, area, AND cost. This is based on information from the associated PDKs and not from PowerPoint slides or press releases.

Competition is what drives the fabless semiconductor ecosystem and I thank Intel and Samsung for the investments they have made. If not for that competitive pressure we would not have the ultra-aggressive FinFET process development schedule nor would we have the competitive wafer pricing I have seen of late. Unfortunately all FinFET processes are not created equal so it will be difficult for the fabless companies to design to multiple foundries which mean there will be clear winners and losers in this game. If this was a horse race and I had to make a bet today it would be TSMC to win, Samsung to place, and Intel will not even show. Just my opinion of course.