TSMC – Page 36 – SemiWiki

December 6, 2014

TSMC Sees More Growth in 2015!

TSMC Sees More Growth in 2015!
by Daniel Nenni on 12-06-2014 at 8:00 pm
Categories: Foundries, TSMC

As I wait for my plane to Taiwan I’m wondering what the New Year has in store for the fabless semiconductor ecosystem. Good things I hope but to make sure let’s take another look at one of my trusted economic bellwethers (TSMC) which I’m guessing will break the $25B revenue mark this year. That is more than a 25% growth rate year over year. What an amazing road this company has paved for us!

Here are some interesting snippets from the TSMC 14th Annual Supply Chain Management Forum held in Hschinsu last week:

Next year the global semiconductor industry will grow 4%-5%
We do not foresee any unusual inventory supply chain adjustment
The global foundry industry is expected to expand 12% in revenue next year from this year
TSMC’s foundry market share will rise to 53% of the global market this year, compared with 49% last year
20 nanometer chips will account for 20% of the firm’s total revenue this quarter
Revenue from 20nm chips should be more than double next year
TSMC is scheduled to begin pilot production of its advanced 10nm technology in Q4 2014 and to ramp up production at the end of 2016
Manufacturing capacity will increase by 12% from last year, with total annual capacity expected to reach 8.2 million 12-inch equivalent wafers in 2014

“TSMC’s success comes from collaborating with our customers and suppliers through our Grand Alliance so that we magnify each others’ innovations and stand together as a most powerful competitive force in the semiconductor industry,” said TSMC Co-Chief Executive Officer Dr. Mark Liu. “Our supplier partners are a critical part of this alliance, and we look forward to reaping the rewards of many years of strong growth together.”

The Outstanding Contribution Award went to Applied Materials for EPI/PVD Equipment and Local Service. From what I heard this is in direct response to the success of the 16FF+ process but more on that later.

One of the things I have enjoyed over the years is the candid nature of Morris Chang’s comments. Even on the quarterly conference calls which are usually scripted. So far I have experienced the same from heir apparent Mark Lui. Take a look at Mark’s resume on the TSMC website:

Dr. Mark Liu is currently President and Co-Chief Executive Officer at Taiwan Semiconductor Manufacturing Company (TSMC). Prior to this, he was Co-Chief Operating Officer from March 2012 to November 2013. Before that, he was Senior Vice President of Operations from 2009 to 2012. From 2006 to 2009, he was a Senior Vice President responsible for the Advanced Technology Business at TSMC. From 1999 to 2000, he was the President of Worldwide Semiconductor Manufacturing Company.

Prior to joining TSMC, from 1987 to 1993, he was with AT&T Bell Laboratory, Holmdel, NJ, as a research manager for the High Speed Electronics Research Laboratory, working on optical fiber communication systems. From 1983 to 1987, he was a process integration manager of CMOS technology development at Intel Corporation, Santa Clara, CA, developing silicon process technologies for Intel microprocessor.

Ph.D., Electrical Engineering and Computer Science, University of California, Berkeley

Some people say filling the shoes of Morris Chang will be difficult but I do not see a problem here. I would hold Mark’s credentials up against any other CEO in the semiconductor industry, absolutely.

Also Read: Intel is NOT Quitting Mobile!

November 25, 2014June 14, 2019

What makes the world smart?

What makes the world smart?
by Pawan Fangaria on 11-25-2014 at 4:00 pm
Categories: Coventor, EDA, Foundries, TSMC

The simple answer is when everything in the world is smart. But if you think deeply, you would find that the continuous progression to make things easy in life is what makes the world smarter day-by-day – the sky is the limit. In the world of computing, consider the 17[SUP]th[/SUP] century era when humanbrain was used as a computer and it took ~200 years when in 19[SUP]th[/SUP] century the first mechanical computer was invented by Charles Babbage considered as father of the computer. Today we are in much advanced state and the pace of innovation is pretty fast. Technology definitely makes things smarter, life easier, and pace of doing things faster.

Today we are talking about IoT which makes all devices around us smart enough to sense and act as programmed by us, whenever and from wherever we want. What makes it possible? Sensor is not a synonym of smart, but it is the technology which enables smart things to be done. Various types of sensors can detect every movement, temperature, pressure, light etc. and activate its device to do something. We often hear talk of a world with a ‘Trillion Sensors’ associated with IoT, and we are getting there….

In 2014 MEC(MIG’s MEMS Executive Congress), Chris Wasden, Executive Director, Sorenson Center for Discovery and Innovation, University of Utah talked about the number of internet devices in use: >5 Billion today and is expected to reach 18B by 2018, and the number of sensors crossing 1 Trillion by 2025. And he talked about platform leaders (device, chip, MEMS etc.) to emerge and MEMS to co-create an industry platform to reach the 1T target.

Interestingly, foundry leaders are taking great interest in MEMS. George Liu, Director, TSMCtalked about multiple technology drivers (Personal, Home, City, Automotive and so on) in the context of IoT as against mainly computers in last several decades. He recognized the importance of sensors in making the devices intelligent and smart and also the gaps (material, architecture, low power, integration, packaging, capacity and price) that need to be filled to bring MEMS into main stream. And how can foundry contribute in filling the gap? Of course supply chain, ROI, scaling and so on, but what caught my attention are sensor and MEMS PDKs and joint process & product development between design and foundry. Wow! This can open up big opportunity for fabless MEMS development. This reminds me about one of my blogs (What will drive MEMS to drive I-o-T and I-o-P?) in which there was emphasis on standardization which can bring MEMS into volume production, and GLOBALFOUNDRIES pursuing the path of IC fab-like production discipline for MEMS.

Getting to 1T sensors is not a slam dunk; like EDA enabled fabless IC development, we need highly sophisticated and integrated automation including modeling to accelerate MEMS development. In the days to come we will see newer and newer MEMS devices, which is beyond our imagination today. But that reality has to be complemented by automated tools which can model the MEMS accurately, integrate them at system or IC level and verify accurately as fast as possible.

Taking at look David Cook’sblogat Coventorwebsite where he mentions about CoventorWare and MEMS+for MEMS+IC co-design, modeling, simulation and analysis, and SEMulator3Dfor virtual fabrication of MEMS devices to cut down on long build-and-test cycles through fab and improve yield before production, I concur with him that these tools are very apt in today’s environment to cater to the complexity of a variety of MEMS, yet meet the shrinking time-to-market window. In fact this reminds me about another blog written by Gunar Lorenz on new capabilities in MEMS+ 5.0– Breakthrough MEMS Models for System and IC Designers.

In MEMS+ 5.0, Reduced Order Models (ROMs) of MEMS devices (which allows writing out snap shots of sophisticated nonlinear multi-physics models into Verilog-A protecting the IP) can be exported into Simulink schematics for system designers and circuit schematics for IC designers. Verilog-A ROMs can run up to 100 times faster than full MEMS+ models in CadenceVirtuoso or MATLABSimulink. Users can decide whether to write out ROMs in Verilog-A for circuit schematic or MROM (a new file format) for Simulink. The environment provides good set of controls for users to tradeoff between accuracy and speed. Simulation results from MROMs can be viewed and animated in 3D, just like results from full MEMS+ models.

Smart tools to develop smart MEMS, smart MEMS to develop smart devices and smart devices to make smart eco-system are must to create a smart world!

Intel 2014 Investor Meeting and 14nm Status

Intel 2014 Investor Meeting and 14nm Status
by Scotten Jones on 11-21-2014 at 6:30 pm
Categories: Foundries, Intel Foundry, TSMC

Intel’s investor meeting was held yesterday and for me the presentation that is most interesting is Bill Holt’s. The presentations are available on the Intel website: Intel Corporation – Presentations Material 2014. Here is the 2013 version of this presentation: Intel Corporation – Presentations Materials 2013. First off I want to vent a little, what is up with the European paper size? Does Intel have a secret plan to get everyone in the US to buy new printers?

On slides 3, 4 and 5, the 14nm yields are shown versus 22nm. The good news for Intel is the yields are finally looking pretty good; the bad news is it has taken a long time to get there. I find it interesting that TSMC is reportedly already getting good yields on their 16nm process suggesting their 16nm/14nm development has proceeded more smoothly than Intel’s. From what I have heard Samsung and Global Foundries continue to struggle with 14nm yields.

On slide 7, 14nm pitches of 42nm for STI, 70nm for gate (GP) and 52nm for M1 (M1P) are presented. This is in contrast to TSMC’s pitches of 48nm for STI, 90nm for GP and 64nm for M1P as reported at IEDM 2013. This gives a GP x M1P of 3,640nm[SUP]2[/SUP] for Intel and 5,760nm[SUP]2[/SUP] for TSMC. I have two observations on this:

[LIST=1]

This is comparing Intel’s 14nm to TSMC 16FF. At the 2014 IEDM on December 15, 2014 TSMC is scheduled to present what looks to be 16FF+. It will be interesting to see what if any pitch improvements they report for 16FF+ versus 16FF and how that compares to Intel. The TSMC 16FF GP and M1P are the same as 20SOC, at the 2014 TSMC technology symposium 16FF+ was reported to offer a 15% improvement over 20SOC so perhaps GP x M1P is something like 4,896. I should note here that I have had someone who should know what they are talking about tells me the 16FF+ does not improve density versus 16FF.

The BEOL pitches for Intel’s 14nm process have started to come out. My understanding is there are 8 layers of 52nm pitch metal produced with Self Aligned Double Patterning (SADP) followed by 80nm and 160nm pitch layers with air gaps and finally 3 layers of presumably large pitch metal. The use of SADP for the first 8 metal layers means they are 1D metal layers and the design rules are very restrictive. It seems unlikely to me that a foundry could get away with such restrictive rules and this is a key part of why Intel can produce smaller metal pitches than anyone else (more on the metal layers later).

Slide 8 shows a 0.54x scaling in SRAM size, an impressive achievement!

Slides 9 through 14 present fin scaling and show scaling to a smaller pitch while simultaneously increasing the fin height. This is another impressive achievement.

Slide 15 presents Intel’s leadership in introducing new process technologies to the industry. Once again these achievements are impressive and it illustrates how much Intel has helped to drive the industry forward over the last decade. The key question this slide doesn’t address is what is next and will Intel maintain a lead. TSMC, Samsung and Global Foundries are all ramping up their FinFET processes and have essentially “caught up” on that innovation. In my opinion the next innovation will be Germanium or Indium Gallium Arsenide fins and it will be interesting to see who get there first.

Slides 18 and 19 present the 14nm Interconnect. I have to say I am very surprised by the 13 layers of interconnect at 14nm (the number of metal layers isn’t listed here and is from other sources). Intel had 6 metal layers for 180nm and 130nm while transitioning from aluminum to copper metallization; at 90nm they had 7 metal layers, 8 metal layers at 65nm and then 9 metal layers at 45nm, 32nm and 22nm. My expectation at 14nm was 10 metal layers. What I think happened was the use of SADP to produce the 52nm critical metal pitches forced 1D metal and a lot of metal layers to accomplish the required interconnect. My “guess’ is:

M1 through M8 are alternating x and y direction metal layers all serving for short signal runs.
M9 and M10 reportedly have air gaps and presumably these are longer signal runs where the air gaps are need to lower the RC delay.
M11, M12 and M13 are presumably large pitch metal runs for power and ground.

Slide 20 is a new version of the “infamous” slide showing Intel’s density lead. In the past the x-axis has been node but has now been switched to time. Now instead of Intel lagging and then pulling ahead they consistently lead. The following is my own version of this slide comparing Intel and TSMC actual processes and then forecasting TSMC 16FF+ with a 15% shrink and 10nm with a 2.2 density improvement based on the TSMC technology symposium early guidance (these are updated projection since my “Who will lead at 10nm post”). For Intel I used my own trend projected 10nm numbers.

Intel Versus TSMC GP x M1P by year of technology introduction.

As can be seen from this plot, Intel consistently leads for density; the problem to me with this analysis is until recently Intel was exclusively using their processes for microprocessors (MPU) which have a much narrower set of performance requirements than processes for foundry use. Intel only had to focus on fast transistors while TSMC has to provide processes that meet a wide variety of different requirements. At 22nm Intel’s MPU and foundry processes have the same pitches for GP and M1P but will that hold at 14nm and if so how many customers will accept the restrictive design rules required for SADP metal layers?

Slides 22 and 23 show Moore’s law is alive and well at least at Intel. The cost per wafer goes up with each generation but the die shrinks more than make up for it. As we have entered the multi-patterning era wafer costs are rising faster than we have historically seen but at least at Intel the die shrinks are overcoming this.

Some observers believe that at the foundries the increase in wafer cost at 20nm due to multi-patterning has overwhelmed the die shrink and die costs have risen. I do not believe this but rather think the die cost reductions have slowed. At the 16nm/14nm node at foundries the wafer costs will again increase (although the use of 20nm backend pitches mitigates this to some extent) and the shrinks are minimal. At 16nm/14nm die cost reductions will be minimal at best. At 10nm I expect foundries to deliver competitive cost per die reductions as we get back to full shrinks, in fact TSMC has guided a 2.2x increase in density. Wafer costs from 16nm to 10nm at TSMC are not going to go up anywhere near 2.2x!

All in all Intel continues to deliver impressive technological progress and do it economically. Comparing Intel with TSMC (or any foundry) for device area is really not a valid comparison until Intel is a substantial foundry player and the processes being compared are both being used in the foundry space.

I am still going through all of the presentations but I also wanted to comment on Stacy Smith’s presentation slide 51 which shows Intel’s fab capacity and demand coming back into balance, which is a really big deal after the low levels of loading seen in 2012 and 2013.

November 12, 2014

Who is REALLY Using TSMC 16FF+?

Who is REALLY Using TSMC 16FF+?
by Daniel Nenni on 11-12-2014 at 7:00 am
Categories: FinFET, Foundries, TSMC

As I wrote last week there is a whole list of companies on LinkedIn with people working on TSMC 16nm. Today TSMC released a list of customers that have risk production 16FF+ silicon. Most of us knew this already but now we can talk about it in more detail. This is a really big deal for the FinFET doubters out there. Just because Intel had all sorts of yield trouble with 14nm does NOT mean that TSMC will experience the same type of issues.

Also Read: Who is Using Samsung 14nm?

According to TSMC the 16FF+ process provides 40% more performance than 20nm or consumes 50% less power at the same speed. The first applications you will see of course are mobile, specifically stated is “high-end mobile” meaning that 16FF+ is much faster than Samsung 14nm. Computing, networking, and consumer applications are also mentioned.

Also Read: Let the FinFET Yield Controversy Begin!

As an example of high performance a 2.3GHz ARM Cortex®-A57 is referenced and for low power a 75mW Cortex-A53. Yield is also mentioned as being ahead of the curve in comparison of all the other TSMC nodes. Remember TSMC used the same metals for 16nm as it did for 20nm which in hindsight was simply brilliant. Solve the double patterning riddle first then add FinFETs and address the added fin variation challenges.

Also Read:Cliff Hou at TSMC OIP

As Cliff Hou mentioned in his keynote at last month’s TSMC OIP Forum, a wide variety of EDA tools and hundreds of process design kits with more than 100 IPs, all of which have been silicon validated, is already supported for 16nm. TSMC also stated that 16FF+ has close to 60 customer designs scheduled to tape out by the end of 2015. Coincidentally, high volume 16FF+ ramp should start in Q3 2015, just in time for the next Apple iPad refresh.

“Our successful ramp-up in 20SoC has blazed a trail for 16FF and 16FF+, allowing us to rapidly offer a highly competitive technology to achieve maximum value for customers’ products,” said TSMC President and Co-CEO, Dr. Mark Liu. “We believe this new process can provide our customers the right balance between performance and cost so they can best meet their design requirements and time-to-market goals.

“TSMC 16FF+ process technology enables Avago to design highly optimized custom silicon solutions for networking applications in cloud datacenters and enterprise networks,” said Hock Tan, President and CEO of Avago Technologies Limited. “TSMC’s 16FF+ process technology in combination with Avago’s industry leading SerDes, memory, processor cores, and design implementation techniques deliver unparalleled time-to-market, performance and power benefits to OEM customers.”

“Sixteen-nanometer FinFET Plus technology provides compelling performance per watt advantages, enabling a myriad wave of market inflection points such as Internet of Things, 5G networks and software defined networks,” said Tom Deitrich, Senior Vice President and General Manager for Freescale‘s Digital Networking group. “Powering the new virtualized network, a new family of Layerscape™ multicore processors using ARM® and Power Architecture® technologies will be Freescale’s first offerings to leverage this innovative process technology.”

“Our collaboration with TSMC on 16FF+ technology will give LG strong competitiveness with respect to power, performance and area in the mobile AP market,” said Bo-ik Sohn, Senior Vice President at LG Electronics. “We believe that the product made through our partnership with TSMC will meet the widespread consumer demand for distinctive mobile technology.”

“TSMC is a trusted technology partner, helping to drive MediaTek’s success over the past decade to deliver market leading SoCs,” said CJ Hsieh, President of MediaTek. “With TSMC’s first ever FinFET 3D architecture and enhanced plus version, MediaTek advances mobile and home entertainment SoCs demonstrating even faster speed, optimized power and reduced chip size. The performance boosts and power reduction for MediaTek’s processors and modem technologies, compared to previous generations, has proven TSMC’s 16FF+ to be a highly competitive process technology for our chipsets.”

“NVIDIA and TSMC have collaborated for more than 15 years to deliver complex GPU architectures on state-of-the-art process nodes,” said Jeff Fisher, Senior Vice President, GeForce Business Unit, NVIDIA. “Our partnership has delivered well over a billion GPUs that are deployed in everything from automobiles to supercomputers. Through working together on the next-generation 16nm FinFET process, we look forward to delivering industry-leading performance and power efficiency with future GPUs and SOCs.”

“Our partnership with TSMC enables us to address evolving semiconductor technologies and to provide state-of-the-art solutions for our customers in the automotive, industrial and ICT fields,” said Hisao Sakuta, Chairman & CEO of RenesasElectronics Corporation. “Now, we want to take full advantage of the 16FF+ technology to deliver added values for our customers in the advanced automotive information and ICT markets.”

“TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results,” said Moshe Gavrielov, President and CEO of Xilinx. “This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry’s highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry’s first All Programmable MPSoC and 3rd Generation 3D ICs.”

About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s owned capacity in 2014 is expected to be about 8.2 million (12-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide both 20nm and 16nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.

More Articles by Daniel Nenni…..

November 10, 2014

Money for data and your MEMS for free

Money for data and your MEMS for free
by Don Dingee on 11-10-2014 at 12:00 am
Categories: Foundries, TSMC

An ongoing IoT debate centers on the notion that just because we can do something does not mean we should. From discussions at the recent MEMS Executive Congress, looking at what TSMC and some others see as the endgame for a trillion sensors signals possible trouble ahead. Continue reading “Money for data and your MEMS for free”

November 9, 2014August 22, 2024

Who is Using Samsung 14nm?

Who is Using Samsung 14nm?
by Daniel Nenni on 11-09-2014 at 7:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

As I have mentioned before, there are very few secrets in Silicon Valley. Just last week I was minding my own business at a Starbucks when I overheard two engineers complaining about Samsung 14nm shuttles being delayed. They had badges on but I won’t out them because it could have easily been any of the fabless companies in Silicon Valley since just about all of them are working with Samsung this time around, even Apple.

Another good source on who is using what foundry at 14nm and 16nm is LinkedIn. If you are a premium member you can do advanced searches for the fabless company of choice with “14nm”, “16nm” or “FinFET” as key search terms. Good thing TSMC chose a different path and named it 16nm so we can get better search results. You will find Apple, Qualcomm, Broadcom, Marvell, Nvidia, AMD, Cisco, LSI, Avago, Oracle, Freescale, Jupiter, SanDisk, etc… all of the leading edge fabless semiconductor companies.

Of course I have > 20k connections so it makes it a bit easier since hundreds of my 1[SUP]st[/SUP] connections are doing FinFETs. I’m told that LinkedIn caps connections at 30k so if you want to connect to me you had better not delay. I’m linked to the majority of the SemiWiki fan base so you can do the math on that one if you really want to know how many registered members we have.

Based on the LinkedIn searches I did, all companies designing with FinFETs are using TSMC 16nm. Most are also using Samsung 14nm but some are TSMC loyal customers, Broadcom, Oracle, and Xilinx to name a few. I couldn’t find a company that is only Samsung 14nm which supports my opinion that Samsung is being used as a price lever against TSMC. Of course when I say Samsung 14nm it includes GlobalFoundries as they have a “copy exact” version running up there in Malta, NY.

Try a “10nm” search and you may be surprised at how many people are working on it already. There is also mention of work at 7nm. You can search “Intel 14nm” and see that only Altera, Tabula, and Achronix are working on it. The other Intel Custom Foundry customers must not be doing the actual AMS and layout work yet or Intel is doing it for them.

The nice thing about Apple is that they have a set annual release schedule which is in September. In order to get wafers in time for a September 2015 iProduct refresh the designs must be taped out in Q4 2014 so fabless semiconductor professionals like myself now know for sure which foundry gets what iProduct next year. It is still fun however to watch the regular journalists go all tabloid on this to get cheap clicks for their advertisements. Some of those same journalists are STILL saying Samsung is providing Apple with 20nm parts which is not true.

Where will Apple Manufacture the next iPhone Brain?
by Daniel Nenni Published on 07-17-2013

The not so nice thing about Apple is that they seem to take unfair advantage of the supply chain. This comes from the legal action between Apple and GTAT over a VERY one sided sapphire display contract that may bankrupt GTAT:

“When GTAT’s management expressed their obvious concerns to Apple regarding the deal terms during the contract negotiations, Apple responded that similar terms are required for other Apple suppliers and that GTAT should: ‘Put on your big boy pants and accept the agreement.’”

Disclaimer: The LinkedIn search engine is not great so results may vary depending on who you are connected to and what type of membership you have.

November 3, 2014

Let the FinFET Yield Controversy Begin!

Let the FinFET Yield Controversy Begin!
by Daniel Nenni on 11-03-2014 at 8:00 am
Categories: FinFET, Foundries, Intel Foundry, TSMC

It never ceases to amaze me how people point fingers and create controversy to cover their mistakes. It happened at 40nm, 28nm, and again at 20nm and now it is time for the regularly scheduled yield controversy. Of course any conversation about semiconductor yield generates clicks for SemiWiki so I’m happy to play along.

It generally starts with a semiconductor equipment manufacturer missing their quarterly numbers then throwing their customers under the yield bus. Just once I would like to hear a CEO say, “Hey, we missed our number, my fault.” Of course they never name the customer so all customers come under suspicion which is exactly what is happening here. This time it is Art Zafiropoulo, CEO of Ultratech:

As we have discussed on past conference calls, the difficult implementation of 3D FinFET microprocessors to high production manufacturing. Once again a major logic manufacturer delayed their FinFET ramp. We had then requested to prepare LSA tools for shipment for the end of the third quarter which was delayed. These LSA shipments for the most part caused our third quarter revenue to be less than projected. These LSA systems have been rescheduled for shipment in the fourth quarter. Due to the continued low yield in FinFET devices for the past two years, we have seen a reduction in new LSA bookings in subsequent shipments…

I’m very sorry you missed your quarterly number Art and that your stock price is less than half what it was in January of last year. I’m also very sorry you have to blame customers using misleading statements such as this. Ramping leading edge process technologies is more difficult with every new node so delays should be expected. How does a CEO of an equipment manufacturer not know this?

Clearly Art is talking about Intel in regards to 3D FinFET microprocessors for which I understand. Last September Intel CEO BK held up a laptop that was powered by a 14nm CPU and claimed silicon would ship by the end of 2013. That chip is now shipping (about 2 Quarters late) with products due in time for the holiday season. It really is an impressive microprocessor so congrats to Intel on this one:Intel?s 14-nm Parts are Finally Here! | Chipworks Blog

Now check out this interpretation of Art’s comments from the Motley Fool’s “Senior” Technology Specialist:

However, after listening to the earnings call of chip equipment vendor Ultratech (NASDAQ: UTEK ) , it’s clear to me that neither TSMC nor Samsung quite has the FinFET transistor structure (which promises higher performing transistors at lower power) figured out. This, as far as I can tell, strongly suggests that Intel’s manufacturing lead remains intact.

Comparing the TSMC manufacturing capabilities to Samsung’s is absurd. These are two VERY different companies so don’t be a fool and lump them together. This “Senior” Technology Specialist owns Intel stock of course.

An interesting note, when comparing the density of Intel’s 14nm process against TSMC it is always pointed out that 16nm uses the 20nm process with FinFETs instead of planar transistors. When talking about yield however it is not mentioned, especially now that 20nm is in full production with a better than expected yield ramp. Weird hu

Semiconductor IP Forecast 2014 – 2020

Semiconductor IP Forecast 2014 – 2020
by Daniel Nenni on 11-01-2014 at 10:00 pm
Categories: IP, TSMC

Given that the majority of my 30+ years in Silicon Valley has revolved around semiconductor IP it should be of no surprise that IP is a big part of SemiWiki and our first book “Fabless: The Transformation of the Semiconductor Industry”. That is also why one of my first round blogger draft choices was IP expert Dr. Eric Esteve. Eric has written 211 IP blogs on SemiWiki thus far garnering close to one million views. Eric had not blogged before SemiWiki but he is the author of the industry standard Interface IP Market Survey which was just updated last month.

According to Eric, Design IP is a niche market worth less than 1% of the semiconductor market but its significance in regards to design enablement is unprecedented. Eric started working in the Interface IP segment in 2005 as marketing director for PLDA. At the same time PLDA was launching the PCI Express gen-1 controller IP and within three years the company revenue multiplied by 3 (PLDA was already 10 years old). Next he worked for Snowbush, the IP division of Gennum, building a five year business plan which required deep knowledge of all protocols (PCI Express, SATA, SuperSpeed USB, HDMI and DDRn). In 2009 Eric started IPnest to better use his IP expertise which was pretty unique at that time. Eric released the first annual “Interface IP Survey and Forecast” in Q2 2009.

Why is this survey unique you may ask? Because you can find information that is not available elsewhere. For example there is an IP vendor ranking by protocol: USB2, USB3, PCIe, DDRn, HDMI, SATA, MIPI, and Ethernet. Eric also compiled a competitive analysis by protocol. For every protocol, you can find price information (for the Controller and for the PHY) and an evaluation of the design start count: the number of PCIe (or USB2, USB3, HDMI etc.) IP sales in 2013, then the total number of ASIC/ASSP design starts that include this protocol. To be able to calculate such a number requires an intimate knowledge of the IP market, absolutely.

Also read:Cliff Hou at TSMC OIP

Before working in the IP business Eric spent 20 years in the ASIC business participating in the IP buying process to support customers and then if you add another 10 years spent essentially on IP you end up with 30+ years of IP experience. During the last five years the Interface IP market segment has doubled in size from $240 million in 2008 to $480 million in 2013. It’s a fast growing market which makes the analysis in this report even more important.

One thing I can tell you is that the foundries rely on this forecast. In regards to the foundation and CPU/GPU IP, the foundries support the IP vendors that their customers work closely with which means TSMC has thousands of IP that needs to be prioritized and silicon proven for the new process nodes.

If you look at IP there is a paradox: Design IP is a niche market, weighing in at $2.5 billion in 2013 which is small if you compare it to the foundry business. But suppress Design IP and probably 70% of the chips processed by the foundries vanishes, which is why foundries take great care in supporting Design IP, and not only hard IP, RTL IP as well. It’s interesting to see that the more successful a foundry is, TSMC for example, the greater care it takes with external IP investing time, money, and resources to make sure the IP ecosystem develops properly. In return, foundry customers can reach production faster which sells more wafers.

After reading the report the only question you will probably have for Eric is this: Is the Interface IP Survey forecast up to 2020 realistic?And the answer is:

“I build a five years forecast since the very first release of the survey. This comes from my experience with Snowbush, as it was one of the key requirements. This year I have based the forecast on the number of commercial design starts (IP sales) by protocols. The first task is to evaluate the TOTAL design starts, and the evolution up to 2020, by protocol. For example, SATA and PCI Express don’t have the same growth behavior, so you need to use the protocol granularity to calculate the ASIC or ASSP design starts. Thus you have to evaluate the pervasion potential for each protocol. Then you have to insert the magic parameter: the “externalization factor”. There is an industry consensus about the fact that IDM and fabless tend to buy certain IP when they used to develop it internally. This is certainly true for Interface IP: this is a standard based IP, it’s pretty difficult for a chip maker to add differentiation. The evaluation is complex, and it’s exactly here that the 30 years’ experience add value! A couple of days ago, I read the first version of the “Interface IP Survey” written in 2009, including a forecast up to 2013. In 2009, I have evaluated the IP market to weight $440 million in 2013. And the result is… $421 million for up-front license only. A forecast with less than 5% error at five years is OK for me!

You can get the latest IP Survey HERE.

October 31, 2014April 10, 2025

Silvaco at the TSMC 2014 Open Innovation Platform

Silvaco at the TSMC 2014 Open Innovation Platform
by Daniel Payne on 10-31-2014 at 7:00 am
Categories: EDA, TSMC

The success of our semiconductor eco-system depends on collaboration, so the annual TSMC OIP Event just held on September 30 at the San Jose Convention Center was a prime example of that. I didn’t attend this year, but I did follow up with Amit Nandaof Silvaco this week to hear about what they presented. As a consultant I’ve worked with Amit before when he was at Barcelona Design Inc., an interesting analog-compiler company, now part of Synopsys.

Many engineers think of Silvaco as suppling only TCAD tools, however that’s not really true because they’ve assembled a custom IC design flow of tools that support many PDKs at TSMC:

EDA Tools for Custom IC Design

AMS designers can build their next IoT products using schematic capture, SPICE circuit simulation, waveform viewing, layout editor, DRC, LVS and parasitic extraction tools. Silvaco’s SPICE circuit simulator is called SmartSpice and it has been upgraded to:

Simulate faster by using a new parallel algorithm
Model certified at 16 nm
ETMI reliability supported
Soft Error Reliability

Improved capacity and performance

Related: Modeling and Analysis of Single Event Effects (SEE)

SmartSpice is used by circuit designers for library, memory and critical path characterization and it also has built-in optimizers.

In SPICE circuit simulation you need to have netlists with extracted parasitics to get the most accurate results, and the 3D RC extractor from Silvaco is called Clever. Memory cell design require accurate parasitics in order to tune RAM performance goals and catch all of the capacitive coupling effects caused by 3D layout structures like FinFETs.

3D structure of an SRAM cell

SPICE models are created by the Utmost IV tool, and many different device types are supported: TFT, UOTFT, BSIM-CMG for FinFETs, HSIM-HV2 for high voltage devices, BJT, SOI, JFET, Diode, FRAM.

TFT example fit plot using the RPI a-Si TFT model

Related: SiC and Si Power Devices

On the TCAD side engineers can virtually model diverse semiconductor technologies for: Displays, Power devices, Optical, FinFET, FD-SOI and even soft error reliability. Victory is the product name for this TCAD modeling and it supports 1D, 2D and 3D.

Related – TCAD to SPICE

I think that you’ll agree that Silvaco has a lot more than just TCAD tools to offer semiconductor engineers today, because circuit simulation and IC CAD tools are also included in their tool flow. Another factor that you need to know about Silvaco is that their tools are affordable compared to the big three in EDA. 2014 marks the 30th year in business for Silvaco, which is quite an accomplishment in this competitive industry.

October 26, 2014

Cliff Hou at TSMC OIP

Cliff Hou at TSMC OIP
by Paul McLellan on 10-26-2014 at 7:00 am
Categories: Foundries, TSMC

I attended Cliff Hou’s keynote at TSMC OIP Forum earlier this month. OIP is a huge undertaking. It currently has over 100 ecosystem partners, 10 technology generations, 7600+ IPs, 60+ EDA tools, 7000+ tech files and 150+ PDKs.

Most of Cliff’s presentation gave details on where TSMC are with the various processes. Of course 20nm and above is all in full production, and we know it is shipping in high volume to both Apple and Qualcomm, among others, since they have said so. In fact there are 12 products that are already function proven on first silicon.

16FF completed full qualification in Q4 2013 and entered production. Over 55 products are planned for tapeout in 2014/5 in mobile, networking, CPU, GPU, FPGA and more. They achieved first silicon success on a network processor for HiSilicon Technologies. It is actually a combination of several chips using TSMC’s CoWoS (chip-on-wafer-on-silicon) 3D technology. The logic chips are built on 16FF process containing 32 Cortex-A57 cores, and the second chip is a 28nm I/O chip.

16FF+ (the “+” is important, it is a different process) is currently in qualification, which is on track. They released V1.0 in August 2014 so designs can start. 16FF+ yield is ahead of plan.

The 16FF+ IP ecosystem is already showing silicon results with various interface and memory IP already completed silicon qualification.

Cliff talked about 10nm. He said that it has industry leading density for the smallest die size. Compared to 16FF+ it has a speed improvement of 25%, a power reduction of 45%, density improvement of 2.2X for logic and 0.45X for SRAM. The key upcoming milestones are:

V0.1 available for design starts Q4 2014
V0.5 available, Q2 2015
Risk production November 2015

Going off the bleeding edge, Cliff talked about TSMC’s ultra-low-power technology, especially targeted at internet of things (IoT) applications:

0.18eLL and 90uLL in production
55ULP, 40ULP and 28ULP will have risk production in 2015
RF and embedded flash features for IoT SoC integration
The ULP processes have lower Vdd to reduce active and standby power. Tailored eHVT device enables over 70% reduction in standby power. Think battery life.

Cliff’s last slide summarized TSMC’s process introduction roadmap:

16FF+ is mature and ecosystem ready with multiple solutions. First product is silicon-proven with 50+ tape-outs are scheduled for 2014 and 2015
10nm offers 2.2X gate density, 25% better speed or 45% power reduction with risk production in Q4 2015. Ecosystem solutions have been developed, certified and in use on test chips
Ultra Low Power technology platform, covering from 0.18ɥm to 28ULP, can support various IoT applications. Existing ecosystem can be leveraged for fast time-to-market