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Life Without EUV: SPIE Day 2

Life Without EUV: SPIE Day 2
by Scotten Jones on 03-29-2015 at 11:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC

I previously published a summary of day 1 of SPIE and I wanted to follow up with observations from successive days.

SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies.Serving more than 256,000 constituents from approximately 155 countries, the not-for-profit society advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors approximately 25 major technical forums, exhibitions, and education programs in North America, Europe, Asia, and the South Pacific. www.spie.org
Tuesday 2/24 – day 2

Optical lithography with and without NGL for single-digit nanometer nodes – Burn Lin, TSMC
The paper began with a discussion of growth in cost per node from the 1.15x per node increase to 1.4x for the latest node. Issues with overlay were really the heart of this paper. The author discussed the many issues that can lead to poor overlay from warpage, back side particles, wafer non linearity due to uneven heating, mask flatness and particles, lens heating and others. The

The move to multi patterning is making overlay an even bigger issue. Overlying multi patterning over single patterning or multi patterning with 3 photo and etch steps on multi patterning with 2 photo and etch steps creates higher order overlay issues.

The authors sees ArFi single exposure limited to approximately an 80nm pitch. Multi pattering gains resolution by pitch splitting but creates cost and overlay issues. He see EUV with an NA > 0.33 as difficult and expensive to achieve as well as k1 < 0.4 being difficult yielding a pitch of 32.4nm, marginal for 7nm, may need some double patterning.

The key to solving the overlay issue according to the author is to go to single exposure and etch at all layers. A table was presented indicating that the least expensive option at N7 is single exposure with Multi beam E Beam (MEB). Interestingly this opinion appears to contrast with the more main stream TSMC approach of using EUV.

The author also discussed Directed Self Assembly (DSA) as a very useful option to reduce costs but one still having CD uniformity plus placement and defect issues.

Also read: EUV Makes Progress and Other Observations From SPIE 2015

Evolving optical lithography without EUV – Donis G. Flagello, Nikon
Nikon has stopped working on EUV leaving it to ASML. I came to this paper very interested to hear what Nikon’s roadmap is to move forward without EUV. I have to say this was one of the more disappointing papers I attended at SPIE. It was long on quirky “Latin like” nomenclatures but short on an actual roadmap.

Relative costs for 193i double and triple patterning versus EUV were presented showing EUV to be more expensive. Continued progress in ArFi scanner throughput was noted with additional increases in wafers per days forecast for 2018. Whereas 3,500 wpd was common in 2010, today 4,000 wpd is common and by 2018 6,000 wpd is forecast.

The author also offered that gains for 450mm are better for ArFi than for EUV.

There was a fair amount of discussion of resolution enhancement techniques that are being sued in optical microscopy and the potential to apply them to lithography. Immersion lithography after all is a lithography application of immersion techniques that have been used in microscopy for decades. This however struck me as a proposal for a research program as opposed to a particle roadmap.

Integration of NAND flash memory ISO multilayer etching to improve productivity – Chang-kwon Oh, SK Hynix
3D NAND is an area of intense interest for me and I am currently working on a blog discussing the impact I expect it to have on the industry.

Some of the key take aways from this paper were that for 2D NAND costs take off at the 1x, 1y and 1z generations. Cell to cell cross talk is also an increasing issue for 1x and subsequent generations.

SK Hynix expects to introduce 3D NAND in 2015.

3D NAND offers improved density, writing speed, endurance and power efficiency. The trade off is productivity, yield and complexity.

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Intel to Buy Altera?

Intel to Buy Altera?
by Paul McLellan on 03-28-2015 at 1:05 pm
Categories: FPGA, Intel Foundry, TSMC

You may already have heard today’s big news in the semiconductor fabless ecosystem that Intel is apparently in talks to buy Altera. I embarrassed myself predicting that Samsung were in talks to buy Freescale (which, of course, they might have been but NXP won that particular race). But this time it is definite enough that the WSJ covered ittoo. Altera had a market cap of $10.4B so this is a big acquisition, up there with the aforementioned NXP/Freescale merger.

The Wall Street types (by which I mean people who work in finance, not the WSJ people) are all trying to predict the effect that this will have on TSMC, since they assume that if the deal is done tomorrow morning that Intel will be making all Altera FPGAs from, maybe, tomorrow evening onwards.

But here is the reality. Altera used TSMC down to 20nm. Then it famously switched to Intel foundry for 14nm. It is right now working on taping out those first parts. On their earnings call they admitted that this was slipping from Q1 to Q2 (to be fair, Xilinx said the same thing about their parts in TSMC 16FF+). I would not in the least bit be surprised to find that they slip further still since I have heard that the program is not going smoothly. Switching from a foundry that truly knows what is doing, TSMC, to one that is just starting in the business, Intel, was never going to be easy.

Once those parts tape out (let’s be generous and keep to the Q2 estimate) they need to be prototyped and then early production parts shipped to customer to design them into things like LTE base-stations or routers, then those systems need to go into manufacturing and get into volume and then Altera will get volume orders. That will be in 2017 or 2018. Until then, every FPGA that Altera ships will be manufactured by TSMC. If that sounds a little unlikely, it is just the same as Intel’s LTE modem line which is also manufactured by TSMC and not in-house at Intel, and is unlikely to be until 2017 it seems. And that is a part that they would dearly love to bring inside since it means they can then integrate it with their application processors for tablets and mobile.

In the meantime, every part shipped by Xilinx will also be manufactured by TSMC (or maybe there are some very old parts still shipping from UMC, Xilinx’s old foundry until 28nm) and every Lattice part will ship from UMC.

This makes it all sound very important but actually the number of wafers that FPGA companies need is not that high compared to anything going into mobile devices.

In my opinion this is really negative for Intel foundry. The implication is that Intel cannot compete in foundry without owning its customers. The only other publicly announced foundry partners for Intel I know of are Tabula (who shut down recently) and Achronix. Both Tabula and Achronix have Intel as an investor, so partially owning their customer. Also they were both in the FPGA business and so compete with Altera. I’m guessing that Achronix will not be happy if this happens.

See also Tabula Closes Its Doors

Another wrinkle. Altera have a close relationship with ARM. In fact their next generation products (the one that Intel will make) contain ARM processors. That was unlikely enough when Intel was the foundry but Altera was the company designing the parts and selling them. If Intel buys Altera then they will be designing, marketing and selling ARM parts. Given Intel’s obsession with Atom (see Intel’s failed mobile strategy) I wonder how that will play out.

See also Pigs Fly. Altera Goes with ARM on Intel 14nm

I talked to Xilinx but after thinking for a bit they decided not to comment. And kudos for Kevin Morris at EE Journal for his piece last year When Intel Buys Altera.

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The Apple A9 Samsung & TSMC Love Triangle

The Apple A9 Samsung & TSMC Love Triangle
by Robert Maire on 03-25-2015 at 10:00 am
Categories: Foundries, Samsung Foundry, TSMC

The Apple A9 drama continues to play out with no certainty!
At the end of the day does it matter?
Will the winner be the loser?
A Comedy, Tragedy or Love Story?
Depends on your view…

Act I Scene I…The stage is set….

We are watching an Italian Opera of a standard love triangle….
The object of desire is the rich and beautiful Princess Iphonia Applelina being pursued by Prince Don Samsune and Count Don Tsemcee. Each is trying to prove their love for the princess. There are rumors swirling around about whom the princess has secretly promised her love and fortune to. The respective villages of the two suitors are both claiming that their nobleman is the one and true love of the princess whose heart has been betrothed to him.

The plot is further complicated by the young and sexy Countess Snap Dragonee from Qualcomia who is trying to steal away both suitors with her charms. In the background, the mysterious Arabian merchant Glabal Faadhil is hoping to have an affair with the princess so that he may get some of the leftovers of her fortunes. Meanwhile the princess has said nothing publicly except that the Crown Ball for her engagement party will be in the fall of the year but no one yet knows who will be on her ARM for the affair. The opera is full of the standard bit players of servants and interested parties who all have an axe to grind and an interest in the outcome. The endless rumor mongering of an opera is at full farce…..

How will this end?
Who will win? and who will lose?
The fat lady has yet to sing……

We still don’t know & we wouldn’t trade on it
We have been back and forth with the trade “rags” in Taiwan and Korea each claiming victory for the local team. This volley started months ago and its still likely too early to tell for sure. Now the latest rumor is that yield issues at Samsung has pushed business in the direction of TSMC. We don’t understand how this is new news as we have been very publicly talking about disappointing yields at Samsung for months now and how it doesn’t make either mathematical of financial sense given the current yields we have heard about.

Analysts are out there touting this as incremental information. Additionally its unclear that no matter what the financial arrangement that Apple would risk the iPhone 6S roll out on unstable process and poor yields. Is the A9 business really fungible?

The reality is that the Samsung 14nm process and the TSMC 16nm process flows are pretty far apart. The TSMC process is much more conservative and more like a warmed over 20nm design with FinFET rather than a full on new process which is closer to the Samsung description. Its not as if the business can be switched back and forth at the drop of a hat. As we have said in the past, Apple could “tape out” two designs, one for Samsung and one for TSMC and follow through to the end but obviously that’s a lot of work. They already have to tape out two designs, one for the A9 and one for the A9X (the Ipad processor) so we would really be talking about 4 potential designs.

Its likely a zero sum game

There is only so much foundry capacity in the world to go around at the leading edge. If it isn’t used for Apple its going to get used for Qualcomm or others. Whoever doesn’t win the Apple business will get Qualcomm’s business, which as far as I can see is not all that shabby.

This is much like all the speculation on Wall Street as to who won the DRAM contract for which phone and which device. In memory there is contract and spot pricing. Though its always nice to have a “locked in” contract , the reality is that the spot market is more profitable over the longer term as contracts are at a substantial discount to the spot market. So, are the DRAM contract winners really the stocks I should buy??

Will the winner be the loser?
Is the winner of Apple’s A9 business the real loser? Given the pricing we would expect and the way Apple treats its suppliers we think we know the answer to that question. So what does the winner get? Bragging rights? You can’t pay the rent or buy new chip tools with bragging rights. Investors seem to want to buy whomever wins the A9 business or whomever wins the DRAM contract but maybe they are buying the real loser in terms of financial performance. Spending this amount of time, ink and internet bandwidth over who has won what percentage of Apple’s business is not as productive nor as accurate a predictor of who the financial winner is or what the stock will be 6 months or a year from now.

Apple’s the real winner here…
Apple is playing its suppliers like a Stradivarius. We wonder when Apple will have its suppliers paying them to supply them parts. Much like the princess, Apple can lead both suitors on ad nauseam. They will kill one another to get to yield faster at better pricing. We wouldn’t cry for Qualcomm either as they get the benefit of Apple pushing the envelope so hard and can fall under Apple’s pricing and technology umbrella.

More like a TV soap opera…..
Whereas a real opera has some sort of an end, even though many end unrequited, this opera will go on almost forever. We will hear daily and weekly updates on the the dalliances of the players and it won’t end when the A9 winner is chosen because then we will have the A10 and A11 and on and on… This is going to be syndicated into endless reruns.

The stocks!
To be clear, we think that its near impossible to draw a very strong correlation between who wins what contract and the stock price. While it may lift revenues and bragging rights, its unclear as to the benefit to the bottom line. As we had mentioned in a previous note we thought that winning a bigger slice of the A9 pie could cause Samsung to choke on it when the semiconductor business is the only one making money there.

Also read: TSMC 2015 Technology Symposium

We continue to think that TSMC has played the smarter game in dealing with Apple and appears to be playing a more predictable, conservative game and remains very, very focused on the bottom line. For the equipment companies we could yet see a sudden rush of orders once the fat lady sings and one of the players actually has to produce the A9 in volume to make the iPhone 6S Crown Ball in the fall of this year. Until there is more clarity, we wouldn’t jerk around our portfolio based upon the rumor du jour as to who has what A9 business or it could wind up as a tragedy……..

Bravo!! Bravo!!

By Robert Maire
Semiconductor Advisors LLC


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TSMC 2015 Technology Symposium

TSMC 2015 Technology Symposium
by Paul McLellan on 03-25-2015 at 7:00 am
Categories: Foundries, TSMC


This year’s North American TSMC Technology Symposium is fast approaching. There are three, starting in Silicon Valley.

  • San Jose on Tuesday April 7th at the San Jose Convention Center
  • Boston on Tuesday April 14th at the Burlington Marriott
  • Austin on Thursday April 16th at the downtown Hilton

The symposium will also take place in Shanghai (date tbd), Hsinchu (tbd), Amsterdam (6/16), Herzliya (6/29), Yokohama (tbd).

Another save-the-date to put on your calendar is the 2015 TSMC OIP Ecosystem Forum which will take place in Santa Clara on 17th September.

What will you hear about if you attend? The current status of all things TSMC and roadmaps for the future. In more detail:

  • update on TSMC’s processes including 16FF+, progress at 10nm, to infinity and beyond
  • specialty technology portfolio including image sensor, embedded flash, power IC, MEMS, and the ultra-low-power ULP processes
  • GIGAFAB ramping capabilities and plans
  • advanced backend technologies including CoWoS, InFO and more
  • OIP (open innovation platform) EDA and IP ecosystem: 16FF+ and 10FF status

Of course, if you are going to attend, you should go all day. But the program for the day (at all 3 locations) is:

  • 8.30 onwards: registration is open
  • 9.35 to 9.50: welcome remarks (Rick Cassidy, President TSMC America)
  • 9.50 to 10.30: industry overview and corporate update (Mark Liu, co-CEO)
  • 10.30 to 10.50: coffee (and ecosystem pavilion will be open)
  • 10.50 to 11.20: technology leadership
  • 11.20 to 11.40: design solution and enablement
  • 11.40 to 12.10: manufacturing excellence
  • 12.10 to 13.10: lunch (and ecosystem pavilion will be open)
  • 13.10 to 14.10: advanced technology updates
  • 14.10 to 14.40: design enablement, flows and services
  • 14.40 to 15.10: coffee (and ecosystem pavilion will be open)
  • 15.10 to 16.10: specialty technology updates
  • 16.10 to 16.40: advanced backend technology
  • 16.40 to 17.30: social hour in the ecosystem pavilion

I will be there. The reason that I think you should be too (assuming you work with TSMC) is that this is one of the very few occasions during the year where you will hear senior TSMC executives talk about their future direction and current status. It is much more compelling, for example, to hear the head of TSMC’s manufacturing talking about fab ramp plans or to hear about 10nm from the head of the organization responsible for developing the process than it is to read a dry press release later in the year.


You can register for the technology symposium here.

“The future of the semiconductor industry is promising with many growth opportunities ahead. To capture these opportunities, we need to continue to work as a collaborative innovation force. Together, we will help each other grow business and stay competitive. This vision is the foundation for the TSMC Grand Alliance. At TSMC, customers are always at the center of all our efforts. With this spirit, TSMC has become our customers’ TRUSTED technology and capacity provider along the way.”

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TSMC ♥ UMC?

TSMC ♥ UMC?
by Daniel Nenni on 03-18-2015 at 8:00 pm
Categories: Foundries, TSMC

The relationship between TSMC and UMC is one of the more interesting ones in the fabless semiconductor ecosystem in my opinion. Both are headquartered in Hsinchu Taiwan and it is very hard to visit one company without seeing the other as they have facilities right across the street from each other. They also share humble beginnings from inside the same incubator (ITRI) so to me TSMC and UMC are brothers.

Industrial Technology Research Institute is a nonprofit R&D organization (incubator) for applied research and technical services based in Taiwan. ITRI is credited with transforming Taiwan’s labor-centric economy into a technology powerhouse originating more than 260 companies including UMC and TSMC. In fact, UMC spun out of ITRI in 1980 as Taiwan’s premier semiconductor company. TSMC spun out in 1987 as the world’s first pure-play foundry and the rest is as they say history.

Having worked with both UMC and TSMC for much of my career I can tell you that they are two very different companies with unique business models. While TSMC has always been a leading edge company, UMC has perfected the “second source” foundry business model like no other. Chartered Semiconductor tried it and failed, SMIC tried it and is failing, Dongbu, X-Fab, Siltera, the list goes on and on… The jury is still out on GlobalFoundries but with the acquisition of the IBM Semiconductor business they have a legitimate claim to leading edge foundry technology, absolutely.

Unfortunately for UMC the foundry landscape has changed. With the re-entrance of leading edge IDM Foundries (Intel and Samsung) technology requirements are moving at a much faster pace and the Capital Expenditure requirements are well out of UMC’s reach. UMC’s CAPEX for 2015 is less than $2B while TSMC’s 2015 CAPEX is greater than $10B! This CAPEX explosion started at 28nm but with FinFETs (16nm and 10nm) plus new devices coming at 7nm the CAPEX requirements will continue to skyrocket as we desperately try to keep up with Moore’s Law.

What is UMC to do?

If you remember, at 28nm UMC joined the Common Platform Fab Club and licensed the IBM Gate-First implementation. Fortunately UMC changed to the Gate-Last version of 28nm which is used by TSMC and is now reaping the rewards of its continued “T-Like” compatibility. I do not see UMC licensing the Samsung version of 14nm like GF did so what choice do they have but to develop their own T-Like 16nm? With the help of TSMC and UMC shared customers: Qualcomm, Texas Instruments, MediaTek, etc…

The alternative of course is for TSMC to license the FinFET technology to UMC in a similar “copy exact” agreement to what Samsung and GF did. Morris change joked that this made GF Samsung’s “accessory” but as you may have read both Apple and Qualcomm pushed for this agreement so it needs to be taken seriously. There is no way the big fabless companies will be satisfied with just one foundry source moving forward. It is no coincidence that Apple is ping ponging between Samsung and TSMC, right?

So what do you think will happen here? Will TSMC help a brother out?

Also Read: Apple Leaks Chip Sources?

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Apple Leaks Chip Sources?

Apple Leaks Chip Sources?
by Daniel Nenni on 03-15-2015 at 10:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

Take a look at the figure below and tell me this information did not come from inside Apple. The question is: Was it voluntary or involuntary? Inquiring minds want to know! There are some minor surprises which I will get to in a minute but the actual source information is spot on to what I have heard the past few quarters. This spicy little piece of information comes from the SemiWiki Semiconductor Process Technology Forum by the way. SemiWiki has always been about crowdsourcing and you will not find a better semiconductor crowd than on SemiWiki.com, absolutely.


In the fabless semiconductor industry there is always a lively debate on who will supply chips to whom. For Apple at 20nm it was TSMC versus Samsung. The Taiwan Press said TSMC and the Korean Press said Samsung. Even after it was clear that TSMC had won the A8 business the Korean press still said Samsung was supplying 20-30% of the chips. The Apple A9 has been all over the map. My prediction was that Samsung would get the A9 since their 14nm LP was ahead of TSMC by 3-6 months and TSMC would get the A9x which jibes with the figure above. I also believe that TSMC has the A10. Samsung having the A10x with 10nm is news to me. It was my understanding that Apple was still evaluating 10nm processes. The 10nm PDKs just came out so I would not bet on this one yet.

The other surprises for me are with the specific process nodes. The A9x should not be using TSMC 16nm, it should be TSMC 16FF+, and the A10 should not be 16nm FF+, it should be a new and improved Apple “tuned” version of 16nm. One interesting note, GlobalFoundries is mentioned as a second source for 14nm but not 10nm and obviously Intel Custom Foundry is nowhere to be seen but more on that later.

Notice that the figure says iPad & MAC for the A9x and A10x? Not really a surprise. In fact, I say it’s about time! Sign me up for six of those as long as they are iOS compatible. I really, really, really am sick of Microsoft Windows!

For the Apple iWatch I agree completely. The S1 is a scaled down version of the A7 which is Samsung 28nm. Given that, it is easy to assume the S2 is a scaled down version of the A8 which is TSMC 20nm.

The baseband processors for the next two versions of the iPhones (iPhone 6s and iPhone 7?) are a bit of a surprise as well. Not the vendors so much (QCOMM and Intel) but the fact that Apple does not have them integrated into the A9 and A10 SoCs. To me this is a total technology fail on their part. And it is not only cost but also power and packaging. As THE leading SoC design company Apple should be publicly shamed for this unless I’m missing something here. Why would Apple not integrate the baseband processor like Qualcomn, MediaTek, and other SoC companies already have?

The takeaway I have from this figure is that Apple is intentionally splitting orders amongst the foundries, not necessarily based on technology, but for business reasons. Clearly Apple wants multiple wafer sources and they will do whatever it takes to make that happen.

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Three Colorful Bytes from the NXP History

Three Colorful Bytes from the NXP History
by Majeed Ahmad on 03-04-2015 at 7:00 pm
Categories: EDA, TSMC

The proposed merger of NXP and Freescale, which creates a bigger semiconductor outfit, also brings forth some fascinating history bytes from the technology heritage that these two spin-offs carry from their respective corporate parents. In 2006, Philips Electronics sold its chip business division Philips Semiconductors to a consortium of private equity investors. The name NXP stood for the consumer’s “next experience.”

Likewise, Motorola Inc. made the Motorola Semiconductor Products Sector autonomous in 2004 and renamed the new silicon-focused outfit as Freescale Semiconductor. This blog traces some parts of the NXP heritage that spans over the past four decades.

NXP: A Fabless Model Pioneer

The Semiwiki Forumuser hist78 has chronicled how TSMC’s Morris Chang found a small audience among semiconductor companies for his revolutionary idea of a pure-play fab back in the mid-1980s. Intel, TI, and Philips gave him a chance to make a presentation, and eventually, both Intel and TI said no.


Philips’ early investment and technology transfer were vital in TSMC success

It was Philips Electronics that agreed to invest and do the technology-transfer to help jumpstart TSMC while owning a 28 percent stake of TSMC during its formative years. Later on, Philips gradually sold all of its shares in TSMC with huge profit, but that’s another story. In retrospect, it was Philips decision to invest in TSMC during the mid-1980s that kick-started the fabless revolution, which in turn, changed the semiconductor landscape forever.

Buy VLSI, Buy SoC

San Jose, California–based VLSI Technology was a pioneer in ASIC, SoC and semiconductor process technologies. It became an early vendor of standard cell ASICs during the early 1980s and dominated the PC chipsets business in the next decade. In 1999, Philips Semiconductors—the precursor of NXP Semiconductors—made a hostile bid for VLSI Technology and eventually acquired the ASIC pioneer for around a billion dollars.


VLSI was an ASIC and SoC pioneer

Apparently, Philips faced difficulties in custom designs quickly moving to new process generations, an area where VLSI excelled with its broad array of chip design libraries and tools. Moreover, the purchase seemed to be stimulated by Philips’ growth and success in the mobile handset chips business. The VLSI buy went a long way for the Dutch company in the unfolding SoC era that followed in the years after this acquisition.

NFC: First Invent, Then Rescue

NXP is a pioneer in near-field communication (NFC) technology; its parent company Philips Electronics developed and launched the contactless access technology in collaboration with Sony back in the early 2000s. The NFC technology was originally developed for the transport and convenience store segments in large Asian cities like Hong Kong and Tokyo. The NFC-based Octopus Card for Hong Kong’s subway service has been a smashing success.


Hong Kong’s Octopus Card: An Early NFC Success Story
(Image: MLP Forums)

But it was tap-to-pay mobile service where NFC was going to make it big. Mobile commerce advocates said that cash would become a thing of the past and that the future of digital money was inside the NFC chip residing in smartphones. However, the promise of mobile payments remained in doldrums until 2014, when Apple and NXP joined hands to develop the first viable tap-to-pay service on the iPhone 6.

Also Read: CDN is Live in Silicon Valley!

Apple Pay—a hugely successful mobile payment service that provided a seal of approval to the NFC technology—used an NXP SoC device that combined the Secure Element (SE) microcontroller with an NFC radio. The SE-centric hardware in the iPhone 6 allowed over-the-air provisioning by the banks and credit card companies and kept mobile operators out of the payment ecosystem.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand Mobile Commerce 2.0: Where Payments, Location and Advertising Converge.

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ASML ASyMptotic progress- When will we get to EUV?

ASML ASyMptotic progress- When will we get to EUV?
by Robert Maire on 02-24-2015 at 5:30 pm
Categories: Foundries, Intel Foundry, Lithography, TSMC

  • ASML making progress – but is it fast enough?
  • ASML has missed 10nm , can it catch 7nm? An economic question
  • Day one at SPIE- Better tone than last year but still cautious

1000 simulated wafers versus 700 simulated
At the opening of the SPIE conference ASML announced that TSMC had reached 1000 wafers a day “exposed” (not printed or produced) by TSMC.

This is significant in two ways; though still just a simulation and not a real test of real wafer production it is a higher theoretical number than the test numbers “leaked” out by IBM over 6 months ago. The second and perhaps more important is that the test was run by a real contender in the semiconductor arms race, TSMC who last year embarrassed ASML at SPIE by announcing that the tool had shot itself in the foot. This would seem to imply that TSMC is more supportive which is also evidenced by their continued purchases of tools.

Is progress fast enough? Zeno’s paradox…
Though progress is clearly being made , we remain concerned that the amount of money and effort being put into EUV is producing fewer and smaller gains as we try to get closer to a “production” system. It would appear much like Zeno’s paradox or an asymptotic curve that incremental progress is slowing as we get closer to the goal.

The announcement of 90 watts of power is certainly better than the 75 watts previously discussed but it would have been a lot better to be talking about a doubling to 150 watts especially as we live in a binary world of Moore’s law.

Catching a moving Moore’s law train … That already left the 10nm station
The reason for our concern about progress rates is that the industry and Moore’s law is not waiting around for EUV to catch up. From discussions with a number of people at the show its clear that 10nm is long gone (as has been known by those in the industry) but the new question is how much, if any, of 7nm can ASML catch. Whereas there never seemed much very serious talk of ASML making 10nm (except by ASML) there is a lot of speculation about a 7nm intercept.

Economics enters the picture
Everything always comes down to the final arbiter of money. This year at SPIE there is clearly more talk about the cost of EUV versus multi-patterning. There was a good presentation of the cost of HiNA (high numerical aperture ) EUV versus multi-patterning.

We have suggested in the past that there should be an economic crossover point from multi-patterning where the EUV production decision becomes clear but it sounds as if that line is blurring a bit. Part of the reason is that the delay in EUV has caused other complications that may confuse the simple economic choice for EUV. One example is the need for multi-patterning in EUV anyway by the time it gets to HVM, thereby taking away one of the positive attributes . However its still hard to see how multi-patterning can win in the long run as we hear talk about quad and “oct” patterning as if they were viable alternatives forever.

It would be wrong to underestimate the semiconductor industry’s aversion to change…..and the industry has gotten very comfortable with multi-patterning.

No Breakthroughs or new news…
There does not appear to be any new news or break through moments so far at SPIE with ASML’s announcement being a ho hum confirmation of the slow pace rather than a positive surprise.

Alternatives not ready
DSA (directed self assembly) , NIL (nano imprint lithography) and direct write E beam lithography are still works in progress further behind than EUV but also not showered in money as EUV has been.

Canon appears to be furthest along with using NIL at Toshiba for NAND production and we wouldn’t be surprised to see it in limited use at some point. The talk of alternative technologies at the show has quieted as discontent with EUV has abated a bit.

Infrastructure not ready
The “ecosystem” for EUV is further behind than EUV itself and will clearly limit the introduction of EUV whenever it really becomes available. This is not new news as we have been talking about it for a long time and the problem has not changed nor have there been any changes in the significant participants, such as KLAC. This remains a major bottleneck for EUV’s progress to HVM.

No stock impact
As there isn’t anything incrementally positive to find at SPIE so far, we see no reason for any significant change in stock valuation. EUV remains a work in progress without a clear insertion point and alternatives have their issues as well.

We do continue to believe that both Lam and AMAT will have a long positive run in etch and dep to support multi-patterning which will clearly be around for quite a while.

Robert Maire
Semiconductor Advisors LLC

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IoT Sensor Node Designs Call for Highly Integrated Flows

IoT Sensor Node Designs Call for Highly Integrated Flows
by Tom Simon on 02-21-2015 at 7:00 pm
Categories: Arm, Cadence, Coventor, EDA, IoT, Mobile, TSMC

Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to the analog circuitry they are connected to. Many MEMS devices are not completely passive: they often have drive systems to keep them in their most linear range of operation. For example an accelerometer will have two comb capacitors, one is for sensing, the other is to control the proof mass.

Cadence, Coventor and ARM recently held a webinar that showed how many important considerations in designing an industrial IoT sensor node can be addressed. The full session is available here.

In these designs the analog circuity needs to be designed and optimized at the same time as the MEMS structures. Chris Welham, Worldwide Applications Engineering Manager at Coventor, points out in the webinar that Coventor offers their MEMS+ product as a vehicle for building 3D design of MEMS elements in conjunction with circuit design tools. The key to making this effective is that after the MEMS designer creates a device, they can export it to Cadence, where it is represented as a parametric simulation model, symbol and PCell. The parameters exposed to the circuit designer are specified when the MEMS+ model is generated. This means that the circuit designer can alter specific parameters of the MEMS device easily and independently. In the webinar Cadence showed how Virtuoso ADE GXL can be used to concurrently optimize the circuit and MEMS parameters to meet the system design spec. The PCell that is produced by MEMS+ produces the necessary layout for mask generation.

IoT sensors need to be compact, rugged and have battery life considerations. These needs often drive the specific packaging configuration for the various SOC’s and MEMS chips in the unit. Designers can utilize BGA, bond wires and TSV’s in an assortment of configurations that can include stacked die with silicon interposer. In the webinar Ian Dennison, Solutions Group Director at Cadence, shows examples of each of the 3D-IC approach alternatives and highlights design and verification aspects of each.

For designs with bond wires, stacked die present special challenges. Manufacturing and coupling noise considerations play a major role in wire placement and shape. Cadence SIP allows wire profiles to be defined and then viewed in 3D. The webinar showed several examples where wire profiles need to be configured to provide adequate clearances to avoid things like overhanging shelves or neighboring wires.

TSV’s offer many advantages over bond wires, but working with them adds complexity to the chip design process. First off, on the plus side, TSV’s reduce overall system cost. On-chip they save routing resources that would otherwise be needed to get signals to the chip boundary and they lower parasitic capacitance and inductance. However the chip floorplan must account for their location. In the webinar Cadence discussed how Encounter and Virtuoso let designers work with TSV’s.

Tim Menasveta, CPU Product Manager at ARM went last but covered the critical aspects of how creating a sensor hub in the IoT sendor device can help the IoT senor meet its many design requirements. Without a hub, all the raw sensors would be transmitting to the aggregation point continuously. This wastes power and bandwidth. Instead with a local processor the IoT sensor node can decide when and what data should be sent. Additionally sensor fusion is extremely important. Many of us are familiar with the necessity of combining the raw inputs from a gyroscope and accelerometer to obtain accurate real world results. Also temperature is an important input for most sensor interpretation. Sensor fusion is useful for dealing vibration or effects of nearby iron objects when calibrating a compass.

The new Cortex-M7 boasts an improved DSP and floating point unit when compared to its predecessor the Cortex-M4. The M7 is ideal for bare metal code. The M8 is more suitable for higher level OS’s. There is also an optional double precision floating point unit available for the M7. To facilitate development of designs using the Cortex-M7, Cadence and ARM have collaborated on an implementation reference methodology built on TSMC’s 40LP process. This design uses Physical IP by the ARM Physical IP Division. It is a low power design that has support for power gating.

The webinar pulled together a wide range of technology, all of which is necessary for putting together leading edge IoT sensor based designs. For a more in depth review of the technology,I suggest following the link at viewing it.

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TSMC 20nm Essentially Worthless?

TSMC 20nm Essentially Worthless?
by Daniel Nenni on 02-15-2015 at 7:00 am
Categories: Foundries, TSMC

It happens at every process node, professional journalists write that something is broken and blames TSMC like a worn out record. To be fair they are not semiconductor professionals with access to the fabless semiconductor rank and file and are easily manipulated which is what happened again at 20nm. Remember when NVIDIA suggested that TSMC 20nm was economically challenged? And the media changed that to “essentially worthless?” Thankfully Apple knew better otherwise we would not have the amazing iProducts we have in our hands today.

Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless
By Joel Hruska on 3/23/2012

Back at 40nm I was the foundry liaison for an IP company and the GPU part of AMD was a big customer. I was the executive sponsor for AMD meaning that whenever there was an escalated problem it landed on my desk. And there were ALWAYS escalated problems at the bleeding edge of GPU design, absolutely.

As 40nm was ramping NVIDIA came out and said their GPUs would be delayed because of yield problems and they pointed fingers at TSMC. The media jumped all over this of course but the AMD guys and I had a good laugh because AMD did not have the same yield problems. At 40nm they had these things called “recommended design rules” (RDRs) to increase yield. One of them was doubling the vias in case there was a one in a billion failure. Of course this increased area and capacitance so the clever NVIDA designers did not do it and had billions of single vias. AMD on the other hand respected the RDRs and beat NVIDIA to 40nm. When the dust settled NVIDIA did admit to design related yield issues but that was not front page news of course.

The same thing happened at 28nm when the fabless guys talked about wafer shortages on conference calls as an excuse for not making their Wall Street targets. The media immediately played the yield card and threw TSMC under the bus. Come to find out TSMC built 28nm capacity based on customer forecasts which were half of what they should have been. TSMC ended up with 100% market share at 28nm versus the 50% forecast and the rest is history.

Nvidia Blames TSMC’s 28nm Process Technology for Slow Sales
by Anton Shilovon 05/11/2012

In March of 2012 NVIDIA came out saying 20nm was not economically feasible and blamed TSMC. In fact, NVIDIA made a detailed presentation at the International Trade Press Conference. The media was all over it reporting in detail WHAT was said but not once considered WHY it was being said and WHY at that particular venue. The entire fabless semiconductor ecosystem had a good laugh because silicon doesn’t lie like people do and the last laugh would be ours.

Some points to ponder:
[LIST=1]

  • Why was this presented at a press conference versus a technical conference?
  • The NVIDIA CEO and TSMC CEO are very close friends, right?
  • The media says GPUs will skip 20nm for 16nm
  • 16nm is really 20nm with low power FinFETs, right?
  • NVIDIA has a 20nm Tegra SoC in production
  • Apple has two 20nm SoCs in production
  • Oracle has a 20nm high performance CPU in production
  • Xilinx has 20nm FPGAs in production

    So tell me, what really happened to the 20nm GPUs?

    Disclaimer: This is written from my aging memory so correct me if I’m wrong here…