TSMC – Page 31 – SemiWiki

May 26, 2015September 1, 2024

Why does Apple do business with Samsung?

Why does Apple do business with Samsung?
by Daniel Nenni on 05-26-2015 at 10:00 pm
Categories: Foundries, Intel Foundry, Mobile, Samsung Foundry, TSMC

The Apple and Samsung relationship is an interesting one. On one hand they have co-developed some of the most innovative products on the market today (iPod, iPhone, iPad, iWatch) yet they are fierce competitors in the mobile market. Some call this type of business relationship “frenemies” others refer to the old Italian proverb “keep your friends close, but your enemies closer.” Personally I refer to it as “foundry business as usual.” Let’s take another look at the Apple/Samsung relationship and see if we can get a better picture of what is really going on here. This of course is based on my experience, observations, and opinions so feel free to correct me if I’m wrong, but I’m not.

Apple became a chip company in the early 1990s with the assistance of VLSI Technology. This was using the ASIC business model where Apple could “toss” an RTL level design over to VLSI and have them deliver finished chips. The first chip was for Apple’s PDA, the Newton, which lost out to the much easier to use BlackBerry and Palm Pilot.

The smartphone (iPhone) was the next device to usher in semiconductor design at Apple. In 2007 the first iPhone was powered by the APL0098 SoC designed by Apple and the newly created Samsung Foundry Division using the same ASIC business model that VLSI Technology pioneered. The first chip used Samsung’s 90nm technology which was one process behind TSMC’s 65nm that offered twice the gate density and a power reduction of up to 50 percent.

The next two iterations of the Apple SoC were released in 2008 and 2009 using Samsung’s 65nm technology. At the same time TSMC was delivering 40nm chips with twice the density of 65nm with significantly reduced power requirements. In 2009, 2010, and 2011 Apple used Samsung’s 45nm which delivered density and power requirements just below TSMC’s 40nm. In 2012 and 2013 Apple used Samsung’s 32nm process but TSMC was already at 28nm which again offered increased density and lower power. At the end of 2013 (iPhone 5+ and iPad Air) Apple used Samsung’s 28nm. Apple also ushered in the 64-bit smartphone with the iPhone 5s beating industry SoC leader Qualcomm.

For the iPhone6 and iPad Air2 in 2014, Apple switched to TSMC’s 20nm which offered a 1.9x density and 25% power advantage over 28nm. The switch from Samsung Foundry to TSMC is a hotly debated topic especially since Apple is now back at Samsung for the 14nm A9 to be released in September of 2015. According to analyst estimates, Apple paid Samsung $2.7 billion for chips in 2014 which is significantly lower than the $4.3 billion Apple paid Samsung in 2013. So yes, the Apple business is a very big deal for the foundries, absolutely.

Apple claimed its semiconductor manufacturing independence with the 2008 acquisition of P.A. Semiconductor and the 2010 acquisition of Intrinsity which enabled them to move from the ASIC business model to the fabless semiconductor powerhouse they are today. If you want my opinion, which clearly you do if you are reading this, Apple bases the process technology decisions on technology and the ability to deliver said technology, simple as that.

I know that Apple evaluated TSMC’s 28nm for the A6 and A6x SoCs but since TSMC was the only foundry yielding at the time TSMC’s 28nm pricing and capacity were in question. At 20nm however, Apple wrote TSMC a very large check to get right-of-first-refusal and most-favored-nation pricing which squeezed out competing SoC vendors (QCOM, MEDIATEK).

At 14nm Samsung developed an LP process specifically for Apple which started risk production in Q4 of 2014 making it viable for the Apple A9 SoC (iPhone 6+) release in Q3 2015. The big shocker here is that Samsung released their own 14nm SoC (Exynos) for their flagship mobile device the Galaxy S6 in the first half of 2015 beating everyone’s 14nm delivery expectations, including my own.

TSMC was two quarters behind Samsung with their higher performance 16nm FinFET++ implementation which will be used in the lower volume Apple A9x SoC business for the iPad refresh in Q4 2015 (the A9 versus A9x volumes are reportedly 70% versus 30%). I also heard that Apple evaluated Intel Custom Foundry 14nm, but to no avail.

10nm will be the next foundry battleground. Samsung and TSMC have both discussed taping out 10nm customer designs in the fourth quarter of 2015 which fits the timeline for Apple’s next product refresh using the A10 and A10x SoCs. Intel on the other hand has been very quiet which is not necessarily a good sign for the competition. Intel surprised the industry with 22nm FinFETs. Another 10nm surprise could certainly be in the making. My guess is that Apple will go to TSMC for 10nm but at this point it is just a guess.

Bottom line: Today, Apple is clearly the most influential foundry customer worth billions of dollars in revenue annually. Apple’s regular product refresh is now driving the foundries harder than I have ever seen and that includes Intel and Samsung. Competition is what makes the fabless semiconductor ecosystem strong and who better than Apple to lead that effort?

May 3, 2015

TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am
Categories: EDA, FinFET, Foundries, IP, TSMC

At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium Suk actually worked for me. In fact, he took over my job running marketing for IC, which is what Cadence called all of the back end tools for both analog and digital. After that he went to Magma (which of course was acquired by Synopsys). At the start of his career he had also, like me, worked for an ASIC semiconductor company, VLSI Technology in my case and LSI Logic for Suk, so we both have what I like to call “silicon in our veins”. That was followed by his first stint at Cadence before going back to semiconductor at Texas Instruments. He joined TSMC six years ago where he is now senior director of design infrastructure marketing, based in Taiwan.

First there are the new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. There are also new standard cell libraries for this process with 9 and 7 track libraries (compared to 12T/9T before). The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). This new process joins the other two ULP processes 55ULP and 40ULP. There is also a library benchmarking kit to help design groups find the best combination of libraries to meet their target PPA.

The design flows are largely in place for both processes. The foundation IP is ready for 28HPC+ with other IP becoming available from now through Q1 of next year. A lot of the IP for 28ULP is still in the planning phase.

Next Suk talked about the 16FF+. The design flows and IP portfolio are all in place with almost everything characterized in silicon. At the event a new 16nm process 16FFC was announced. This is intended for cost-sensitive consumer applications. The foundation IP should be available in Q4 of this year, with interface IP coming in Q2 of 2016.

There was a lot of detailed information about 10nm which TSMC were talking about for the first time.

EDA tool support is as follows:

Automatic Place & Route: Synopsys, Cadence, Mentor
DRC: Synopsys, Cadence, Mentor
LVS: Synopsys, Cadence, Mentor
RCX: Synopsys, Cadence, Mentor
STA: Synopsys, Cadence
EM/IR: Synopsys, Cadence, Ansys
SPICE: Synopsys, Cadence, Mentor
FastSpice: Synopsys, Cadence, Mentor
Custom Design: Synopsys, Cadence

The IP library for 10FF is targeted at several different application areas: smartphone, tablet/ultrabook, networking, CPU/GPU/FPGA. The various IP very in their state of readiness from being full characterized from silicon test chips, or waiting for silicon characterization (but able to be used in design starts), to blocks that are still in development. In detail, IP for 10FF is available as follows:

Standard cell: silicon report
GPIO/ESD: silicon report
PLL: pre-silicon design kit
SRAM compiler: silicon report
ROM compiler: in development
Electrical fuse: silicon report
OTP: in development
DDR4: pre-silicon design kit
LPDDR4: pre-silicon design kit
PCIe: pre-silicon design kit G3 & G4
MIPI: pre-silicon design kit G2 & G3
SATA II/III: in development
10G serdes: in development
USB 2/3: pre-silicon design kit
HDMI/MHL/DP: in development

The 3DIC technologies offer offer heterogeneous die stacking and packaging solutions for high speed, high density and low cost applications. There is thru-silicon-via (TSV) implementation with accurate modeling, an integrated 3D testing methodology, wide-IO interface signal integrity and chip-package-system thermal analysis. The design flow is completely ready, with design kits ready.

TSMC has the broadest IP portfolio in the industry with IP from 0.35um down to 10nm with nearly 9000 different IP titles.

The China Symposium is next week in Shanghai on 5/7 (in Chinese). European symposia are in Amsterdam on 6/16 and Herzliya on 6/29. The TSMC symposium page is here. There will be one in Yokohama but the date is not yet decided. But save the date 9/19 for the OIP Ecosystem Forum in Santa Clara. Details are here.

April 28, 2015

Motley Fooled by FinFETs!

Motley Fooled by FinFETs!
by Daniel Nenni on 04-28-2015 at 10:00 pm
Categories: FinFET, Foundries, Intel Foundry, TSMC

There was an article on Motley Fool recently detailing Intel’s 14nm FinFETs and comparing them to TSMC. Unfortunately the author has zero semiconductor education or experience even though he writes with authority on all things semiconductor. He also has no shame in using outdated papers from conferences he did not even attend to make his misguided point. The things people do for a penny per click… and yes I did speak to him privately about this but he stands by his article and left it to me to prove him wrong, which is why I write this now.

Intel Corporation to Detail 14-Nanometer System-on-Chip Technology at VLSI Symposium

According to SemiWiki experts, Motley Fool’s article misrepresents some of the intricacies associated with FinFets and how drive currents are defined. On the face of it, Intel’s 14nm announcement looks impressive; 37-50% drive current improvements over 22nm, who could complain about that? Unfortunately a slightly deeper dive reveals some issues with this conclusion. Intel, at various meetings, including their analyst meeting back in November 2014, proudly announced their fin pitch scaled from 60nm to 42nm, while their fin height increased from 34nm to 42nm. All good assuming I have similar current/micron of fin perimeter (also called Weff which for one fin is 2* height + top width, but more on that later). With more fins/micron and taller fins, I should be able to have much better performance.

However, if you read their IEDM 2014 paper carefully, you will notice that all Intel’s drive current numbers are quoted per micron of drawn width, i.e. for one micron of top view silicon width. Now taking the assumption above of same current/micron of fin perimeter, how much performance improvement should I get per drawn micron? Using Intel’s own numbers, we have 60/42 =1.43X more fins/micron and fins are 42/34 = 1.24X taller, so all in all we should get 1.76X more drive current/drawn micron. In others words, at equal drive current per micron of fin perimeter, we should have seen 76% more current from these tighter taller fins, but Intel is reporting only 37-50%. Clearly the drive current per effective micron is going down. Intel struggled with their 14nm yield, this suggests they may have also struggled with their device performance.

The article goes on to compare Intel to TSMC 16nm FinFet however the author does not realize that the TSMC 2013 IEDM paper was quoting drive currents/Weff as described above, not per drawn micron. TSMC actually pointed this out in their 2014 IEDM presentation. TSMC also showed even better performance in their 2014 paper than the earlier 2013 version, hence the new process name 16FF+. So in the end, how do they stack up? If you use the Intel’s per drawn micron metric, TSMC 16FF+ has ~10% more drive current than Intel 14nm (all other things being equal including leakage and voltage). If you use another metric like current/fin, or current/Weff, TSMC has an even stronger advantage.

That is why during the TSMC symposium last month Dr. BJ Woo emphatically stated TSMC had “the best” transistor in the 14-16nm technologies. It will be interesting to watch how this unfolds as 10nm process details are disclosed. In my 30 years in the semiconductor industry I don’t remember a more exciting time, absolutely.

April 11, 2015

TSMC Unleashes Aggressive 28nm Strategy!

TSMC Unleashes Aggressive 28nm Strategy!
by Daniel Nenni on 04-11-2015 at 10:00 pm
Categories: Foundries, TSMC

The most interesting presentation at the jam-packed TSMC Symposium last week for me was “Advanced Technology Updates” by Dr. BJ Woo. Coincidentally, I met with BJ during my last visit to Fab 12. Much of what we discussed was about TSMC being more aggressive this year but I wasn’t able to really connect the dots until her presentation. The example I will use here is 28nm but it certainly applies to all of the TSMC process nodes moving forward.

First let me tell you that BJ is engaging and a very credible semiconductor executive. She spent the majority of her 30 year career at Intel in Santa Clara designing both DRAM and microprocessors (she has 13 patents). In 2009 BJ joined TSMC taking responsibility for the advanced technology roadmap at 28nm and 20nm and today is Vice President of Business Development.

According to recent press releases and the resulting comments by analysts, who don’t know any better, other foundries are eating away at TSMC’s 28nm stronghold. Articles like that will get you lots of clicks but they are misleading. Remember, there are two versions of 28nm: gate-first and gate-last HKMG. Moving a TSMC gate-last 28nm design that is in production with 90%+ yield to a new gate-first process is absolute madness. Even moving a production design to a new gate-last process that is supposedly “T” compatible (UMC and SMIC) is risky. But of course it will happen because if you are negotiating a better price from one vendor you have to actually be in the position to use another vendor to even be at the negotiation table.

Having the best yielding process does not just give you the lowest cost, it also gives you better design margins and that is the point TSMC made at the symposium. Today TSMC has five versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), and LP (low power). Two additional processes were added: HPC+ which is an even faster version of HP and ULP which is ultra-low power for IoT and other battery powered applications.

28HPC+ is more compact with 9 and 7 track cell libraries versus 12 and 9 track for 28HPC. The design rules are the same but it has better design margins which offers 15% more performance. 28ULP looks a lot like 55ULP and 40ULP that are already in production. Compared to the associated LP processes, ULP processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption resulting in a 2x-10x increased battery life. IoT and wearable devices are the target applications for ULP processes of course.

The other big 28nm announcement that BJ made is that the TSMC 28nm is now qualified for automotive work which is an industry first. Given the growth of electronics in our cars and the coming autonomous vehicles this is a very big deal for sure.

In the same vein, BJ also talked about a new 16nm process coming called 16FFC, the C meaning compact. It is a more economical version of 16FF+ aimed at cost and power sensitive markets. Power is said to decrease by more than 50% and the pricing will be very competitive for mainstream markets.

Again, when I met with BJ she said TSMC would be very aggressive moving forward and she had a definite twinkle in her eye and now I know why. What a great year for the fabless semiconductor ecosystem, absolutely!

ANSYS Enters the League of 10nm Designs with TSMC

ANSYS Enters the League of 10nm Designs with TSMC
by Pawan Fangaria on 04-09-2015 at 7:00 pm
Categories: Ansys, Inc., EDA, Foundries, TSMC

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award. Read “ANSYS Tools Shine at FinFET Nodes!”. Just before this Intel also certified ANSYS tools at 14nm Tri-gate process as written in another article, “Intel & ANSYS Enable 14nm Chip Production”. And this week, TSMC has certified ANSYS Power Integrity and Electromigration (EM) solutions for 10nm FinFET process node. It’s amazing progress! Read the press release here.

ANSYS portfolio of products was showcased in the TSMC Technology Symposium held in San Jose, California on 7[SUP]th[/SUP] April, 2015. ANSYS’ RedHawk and Totem were certified by TSMC for 10nm FinFET DRM and Spice models. These tools were certified to provide solutions for static and dynamic voltage drop analysis and advanced signal and power EM verification that are required for ultra-low power and high performance SoC designs at 10nm for mobile, computing and networking applications.

At 10nm process node the devices are left with extremely low noise and reliability margins and FinFET’s structure is typically prone to increasing self-heat.

As shown in the picture, heating happens at the device (FEOL) as well as interconnect (BEOL) levels and hence both need to be considered. At sub-28nm process nodes, as we go down the node, the current density increases and makes the device increasingly vulnerable to EM. In a FinFET the current density can be generally 25% more than that in a planar transistor. Also the narrow 3D fin structure and the lower thermal conductivity of the SiO2 dominated substrate can cause local heat to get trapped.

With such tough challenges and extremely tight window of accuracy, it’s critical to ensure power integrity across the chip, package and board. And an accurate EM analysis at all levels is a must. There are some key critical enhancements added into ANSYS tools to provide the kind of accuracy and versatility needed for the EM, power integrity and reliability solution at 10nm.

To support multi-patterning technology, ANSYS solution provides color-aware resistance extraction and EM analysis capability. And there is a complete system-to-block level EM analysis flow with color-aware metal-fill capability that delivers higher yield and performance along with accurate EM analysis.

To address the increasing difference in the current between signal and power rails, ANSYS solution provides various approaches to apply appropriate EM rating factors for signal and power analysis. At 10nm, there can be measurement issue between the drawn trapezoidal shape and the physical implementation of a wire in silicon. ANSYS provides a comprehensive wire width adjustment solution to compensate for the difference that leads to more accurate results in the EM analysis.

ANSYS solution provides thermal-aware EM methodology. Above diagram shows the Thermal-aware EM Flow at TSMC for the 16nm FF+ process node that uses RedHawk, Totem and Sentinel-TI. RedHawk/Totem along with Sentinel-TI uses foundry data to accurately compute the self-heat temperature on an IP or SoC. The temperature can be analyzed at instance or metal layer basis. A Chip Thermal Model (CTM) is generated for back-annotation into RedHawk or Totem. This methodology helps avoiding over-heating of the device, thus increasing its lifetime and reliability.

With increasing complexity and sizes of SoCs at lower nodes, challenge of managing capacity, performance, and parasitic effects also increases. RedHawk/Totem uses a novel Distributed Machine Processing (DMP) capability that can handle large power delivery network (PDN) and perform flat simulation with high performance and small memory footprint. RedHawk-CPA provides chip-package co-simulation and co-analysis within a unified environment that ensures integrity of power delivery on the complete chip and takes into account the impact of package parasitic, thus avoiding undesired hotspots.

The overall comprehensive solution provided by ANSYS delivers highly accurate results as needed at 10nm FinFET node and also reduces design turnaround time through its innovative methodology, algorithms, and multi-physics simulations. The Power Integrity and EM solutions are ready for 10nm FinFET based early design start. On earlier technologies, ANSYS solution for SoC/IP power integrity, noise, and reliability sign-off has been proven on thousands of successful silicon wins.

April 7, 2015

TSMC Processes Galore

TSMC Processes Galore
by Paul McLellan on 04-07-2015 at 10:00 pm
Categories: Foundries, TSMC

Today was TSMC’s 2015 North American Technology Symposium. They talked about a lot of things but perhaps the most important was that they gave a lot of details of new processes, new fabs, and volume ramps.
Continue reading “TSMC Processes Galore”

March 29, 2015

Life Without EUV: SPIE Day 2

Life Without EUV: SPIE Day 2
by Scotten Jones on 03-29-2015 at 11:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC

I previously published a summary of day 1 of SPIE and I wanted to follow up with observations from successive days.

SPIE, the international society for optics and photonics, was founded in 1955 to advance light-based technologies.Serving more than 256,000 constituents from approximately 155 countries, the not-for-profit society advances emerging technologies through interdisciplinary information exchange, continuing education, publications, patent precedent, and career and professional growth. SPIE annually organizes and sponsors approximately 25 major technical forums, exhibitions, and education programs in North America, Europe, Asia, and the South Pacific. www.spie.org
Tuesday 2/24 – day 2

Optical lithography with and without NGL for single-digit nanometer nodes – Burn Lin, TSMC
The paper began with a discussion of growth in cost per node from the 1.15x per node increase to 1.4x for the latest node. Issues with overlay were really the heart of this paper. The author discussed the many issues that can lead to poor overlay from warpage, back side particles, wafer non linearity due to uneven heating, mask flatness and particles, lens heating and others. The

The move to multi patterning is making overlay an even bigger issue. Overlying multi patterning over single patterning or multi patterning with 3 photo and etch steps on multi patterning with 2 photo and etch steps creates higher order overlay issues.

The authors sees ArFi single exposure limited to approximately an 80nm pitch. Multi pattering gains resolution by pitch splitting but creates cost and overlay issues. He see EUV with an NA > 0.33 as difficult and expensive to achieve as well as k1 < 0.4 being difficult yielding a pitch of 32.4nm, marginal for 7nm, may need some double patterning.

The key to solving the overlay issue according to the author is to go to single exposure and etch at all layers. A table was presented indicating that the least expensive option at N7 is single exposure with Multi beam E Beam (MEB). Interestingly this opinion appears to contrast with the more main stream TSMC approach of using EUV.

The author also discussed Directed Self Assembly (DSA) as a very useful option to reduce costs but one still having CD uniformity plus placement and defect issues.

Also read: EUV Makes Progress and Other Observations From SPIE 2015

Evolving optical lithography without EUV – Donis G. Flagello, Nikon
Nikon has stopped working on EUV leaving it to ASML. I came to this paper very interested to hear what Nikon’s roadmap is to move forward without EUV. I have to say this was one of the more disappointing papers I attended at SPIE. It was long on quirky “Latin like” nomenclatures but short on an actual roadmap.

Relative costs for 193i double and triple patterning versus EUV were presented showing EUV to be more expensive. Continued progress in ArFi scanner throughput was noted with additional increases in wafers per days forecast for 2018. Whereas 3,500 wpd was common in 2010, today 4,000 wpd is common and by 2018 6,000 wpd is forecast.

The author also offered that gains for 450mm are better for ArFi than for EUV.

There was a fair amount of discussion of resolution enhancement techniques that are being sued in optical microscopy and the potential to apply them to lithography. Immersion lithography after all is a lithography application of immersion techniques that have been used in microscopy for decades. This however struck me as a proposal for a research program as opposed to a particle roadmap.

Integration of NAND flash memory ISO multilayer etching to improve productivity – Chang-kwon Oh, SK Hynix
3D NAND is an area of intense interest for me and I am currently working on a blog discussing the impact I expect it to have on the industry.

Some of the key take aways from this paper were that for 2D NAND costs take off at the 1x, 1y and 1z generations. Cell to cell cross talk is also an increasing issue for 1x and subsequent generations.

SK Hynix expects to introduce 3D NAND in 2015.

3D NAND offers improved density, writing speed, endurance and power efficiency. The trade off is productivity, yield and complexity.

March 28, 2015

Intel to Buy Altera?

Intel to Buy Altera?
by Paul McLellan on 03-28-2015 at 1:05 pm
Categories: FPGA, Intel Foundry, TSMC

You may already have heard today’s big news in the semiconductor fabless ecosystem that Intel is apparently in talks to buy Altera. I embarrassed myself predicting that Samsung were in talks to buy Freescale (which, of course, they might have been but NXP won that particular race). But this time it is definite enough that the WSJ covered ittoo. Altera had a market cap of $10.4B so this is a big acquisition, up there with the aforementioned NXP/Freescale merger.

The Wall Street types (by which I mean people who work in finance, not the WSJ people) are all trying to predict the effect that this will have on TSMC, since they assume that if the deal is done tomorrow morning that Intel will be making all Altera FPGAs from, maybe, tomorrow evening onwards.

But here is the reality. Altera used TSMC down to 20nm. Then it famously switched to Intel foundry for 14nm. It is right now working on taping out those first parts. On their earnings call they admitted that this was slipping from Q1 to Q2 (to be fair, Xilinx said the same thing about their parts in TSMC 16FF+). I would not in the least bit be surprised to find that they slip further still since I have heard that the program is not going smoothly. Switching from a foundry that truly knows what is doing, TSMC, to one that is just starting in the business, Intel, was never going to be easy.

Once those parts tape out (let’s be generous and keep to the Q2 estimate) they need to be prototyped and then early production parts shipped to customer to design them into things like LTE base-stations or routers, then those systems need to go into manufacturing and get into volume and then Altera will get volume orders. That will be in 2017 or 2018. Until then, every FPGA that Altera ships will be manufactured by TSMC. If that sounds a little unlikely, it is just the same as Intel’s LTE modem line which is also manufactured by TSMC and not in-house at Intel, and is unlikely to be until 2017 it seems. And that is a part that they would dearly love to bring inside since it means they can then integrate it with their application processors for tablets and mobile.

In the meantime, every part shipped by Xilinx will also be manufactured by TSMC (or maybe there are some very old parts still shipping from UMC, Xilinx’s old foundry until 28nm) and every Lattice part will ship from UMC.

This makes it all sound very important but actually the number of wafers that FPGA companies need is not that high compared to anything going into mobile devices.

In my opinion this is really negative for Intel foundry. The implication is that Intel cannot compete in foundry without owning its customers. The only other publicly announced foundry partners for Intel I know of are Tabula (who shut down recently) and Achronix. Both Tabula and Achronix have Intel as an investor, so partially owning their customer. Also they were both in the FPGA business and so compete with Altera. I’m guessing that Achronix will not be happy if this happens.

The Apple A9 Samsung & TSMC Love Triangle

The Apple A9 Samsung & TSMC Love Triangle
by Robert Maire on 03-25-2015 at 10:00 am
Categories: Foundries, Samsung Foundry, TSMC

The Apple A9 drama continues to play out with no certainty!
At the end of the day does it matter?
Will the winner be the loser?
A Comedy, Tragedy or Love Story?
Depends on your view…

Act I Scene I…The stage is set….

We are watching an Italian Opera of a standard love triangle….
The object of desire is the rich and beautiful Princess Iphonia Applelina being pursued by Prince Don Samsune and Count Don Tsemcee. Each is trying to prove their love for the princess. There are rumors swirling around about whom the princess has secretly promised her love and fortune to. The respective villages of the two suitors are both claiming that their nobleman is the one and true love of the princess whose heart has been betrothed to him.

The plot is further complicated by the young and sexy Countess Snap Dragonee from Qualcomia who is trying to steal away both suitors with her charms. In the background, the mysterious Arabian merchant Glabal Faadhil is hoping to have an affair with the princess so that he may get some of the leftovers of her fortunes. Meanwhile the princess has said nothing publicly except that the Crown Ball for her engagement party will be in the fall of the year but no one yet knows who will be on her ARM for the affair. The opera is full of the standard bit players of servants and interested parties who all have an axe to grind and an interest in the outcome. The endless rumor mongering of an opera is at full farce…..

How will this end?
Who will win? and who will lose?
The fat lady has yet to sing……

We still don’t know & we wouldn’t trade on it
We have been back and forth with the trade “rags” in Taiwan and Korea each claiming victory for the local team. This volley started months ago and its still likely too early to tell for sure. Now the latest rumor is that yield issues at Samsung has pushed business in the direction of TSMC. We don’t understand how this is new news as we have been very publicly talking about disappointing yields at Samsung for months now and how it doesn’t make either mathematical of financial sense given the current yields we have heard about.

Analysts are out there touting this as incremental information. Additionally its unclear that no matter what the financial arrangement that Apple would risk the iPhone 6S roll out on unstable process and poor yields. Is the A9 business really fungible?

The reality is that the Samsung 14nm process and the TSMC 16nm process flows are pretty far apart. The TSMC process is much more conservative and more like a warmed over 20nm design with FinFET rather than a full on new process which is closer to the Samsung description. Its not as if the business can be switched back and forth at the drop of a hat. As we have said in the past, Apple could “tape out” two designs, one for Samsung and one for TSMC and follow through to the end but obviously that’s a lot of work. They already have to tape out two designs, one for the A9 and one for the A9X (the Ipad processor) so we would really be talking about 4 potential designs.

Its likely a zero sum game

There is only so much foundry capacity in the world to go around at the leading edge. If it isn’t used for Apple its going to get used for Qualcomm or others. Whoever doesn’t win the Apple business will get Qualcomm’s business, which as far as I can see is not all that shabby.

This is much like all the speculation on Wall Street as to who won the DRAM contract for which phone and which device. In memory there is contract and spot pricing. Though its always nice to have a “locked in” contract , the reality is that the spot market is more profitable over the longer term as contracts are at a substantial discount to the spot market. So, are the DRAM contract winners really the stocks I should buy??

Will the winner be the loser?
Is the winner of Apple’s A9 business the real loser? Given the pricing we would expect and the way Apple treats its suppliers we think we know the answer to that question. So what does the winner get? Bragging rights? You can’t pay the rent or buy new chip tools with bragging rights. Investors seem to want to buy whomever wins the A9 business or whomever wins the DRAM contract but maybe they are buying the real loser in terms of financial performance. Spending this amount of time, ink and internet bandwidth over who has won what percentage of Apple’s business is not as productive nor as accurate a predictor of who the financial winner is or what the stock will be 6 months or a year from now.

Apple’s the real winner here…
Apple is playing its suppliers like a Stradivarius. We wonder when Apple will have its suppliers paying them to supply them parts. Much like the princess, Apple can lead both suitors on ad nauseam. They will kill one another to get to yield faster at better pricing. We wouldn’t cry for Qualcomm either as they get the benefit of Apple pushing the envelope so hard and can fall under Apple’s pricing and technology umbrella.

More like a TV soap opera…..
Whereas a real opera has some sort of an end, even though many end unrequited, this opera will go on almost forever. We will hear daily and weekly updates on the the dalliances of the players and it won’t end when the A9 winner is chosen because then we will have the A10 and A11 and on and on… This is going to be syndicated into endless reruns.

The stocks!
To be clear, we think that its near impossible to draw a very strong correlation between who wins what contract and the stock price. While it may lift revenues and bragging rights, its unclear as to the benefit to the bottom line. As we had mentioned in a previous note we thought that winning a bigger slice of the A9 pie could cause Samsung to choke on it when the semiconductor business is the only one making money there.

Also read: TSMC 2015 Technology Symposium

We continue to think that TSMC has played the smarter game in dealing with Apple and appears to be playing a more predictable, conservative game and remains very, very focused on the bottom line. For the equipment companies we could yet see a sudden rush of orders once the fat lady sings and one of the players actually has to produce the A9 in volume to make the iPhone 6S Crown Ball in the fall of this year. Until there is more clarity, we wouldn’t jerk around our portfolio based upon the rumor du jour as to who has what A9 business or it could wind up as a tragedy……..

Bravo!! Bravo!!

By Robert Maire
Semiconductor Advisors LLC

March 25, 2015

TSMC 2015 Technology Symposium

TSMC 2015 Technology Symposium
by Paul McLellan on 03-25-2015 at 7:00 am
Categories: Foundries, TSMC

This year’s North American TSMC Technology Symposium is fast approaching. There are three, starting in Silicon Valley.

San Jose on Tuesday April 7th at the San Jose Convention Center
Boston on Tuesday April 14th at the Burlington Marriott
Austin on Thursday April 16th at the downtown Hilton

The symposium will also take place in Shanghai (date tbd), Hsinchu (tbd), Amsterdam (6/16), Herzliya (6/29), Yokohama (tbd).

Another save-the-date to put on your calendar is the 2015 TSMC OIP Ecosystem Forum which will take place in Santa Clara on 17th September.

What will you hear about if you attend? The current status of all things TSMC and roadmaps for the future. In more detail:

update on TSMC’s processes including 16FF+, progress at 10nm, to infinity and beyond
specialty technology portfolio including image sensor, embedded flash, power IC, MEMS, and the ultra-low-power ULP processes
GIGAFAB ramping capabilities and plans
advanced backend technologies including CoWoS, InFO and more
OIP (open innovation platform) EDA and IP ecosystem: 16FF+ and 10FF status

Of course, if you are going to attend, you should go all day. But the program for the day (at all 3 locations) is:

8.30 onwards: registration is open
9.35 to 9.50: welcome remarks (Rick Cassidy, President TSMC America)
9.50 to 10.30: industry overview and corporate update (Mark Liu, co-CEO)
10.30 to 10.50: coffee (and ecosystem pavilion will be open)
10.50 to 11.20: technology leadership
11.20 to 11.40: design solution and enablement
11.40 to 12.10: manufacturing excellence
12.10 to 13.10: lunch (and ecosystem pavilion will be open)
13.10 to 14.10: advanced technology updates
14.10 to 14.40: design enablement, flows and services
14.40 to 15.10: coffee (and ecosystem pavilion will be open)
15.10 to 16.10: specialty technology updates
16.10 to 16.40: advanced backend technology
16.40 to 17.30: social hour in the ecosystem pavilion

I will be there. The reason that I think you should be too (assuming you work with TSMC) is that this is one of the very few occasions during the year where you will hear senior TSMC executives talk about their future direction and current status. It is much more compelling, for example, to hear the head of TSMC’s manufacturing talking about fab ramp plans or to hear about 10nm from the head of the organization responsible for developing the process than it is to read a dry press release later in the year.

You can register for the technology symposium here.

“The future of the semiconductor industry is promising with many growth opportunities ahead. To capture these opportunities, we need to continue to work as a collaborative innovation force. Together, we will help each other grow business and stay competitive. This vision is the foundation for the TSMC Grand Alliance. At TSMC, customers are always at the center of all our efforts. With this spirit, TSMC has become our customers’ TRUSTED technology and capacity provider along the way.”