Last week Intel held a manufacturing day where they revealed a lot of information about their 10nm process for the first time and information on competitor processes continues to slowly come out as well. I thought it would be useful to summarize what we know now, especially since some of what Intel announced was different than what I previously forecast.
Continue reading “14nm 16nm 10nm and 7nm – What we know now”
Integrated Photonics Accelerates with Entrance of TSMC and TowerJazz Foundries
I’m writing this from the Boston airport on my way home from four straight weeks of PIC (photonic integrated circuit) related travel. It’s been a grueling but very rewarding four weeks and the big take away from this month is that there are now many more signs in the market that integrated photonics is reaching a real tipping point.
I started off March by traveling to Brussels, Belgium to attend the PIC International Conference. This was PIC International’s second year and attendance grew from 440 attendees last year to over 550 this year. This was echoed at the Optical Fiber Conference held in Los Angeles which boasted 14,500 attendees and over 663 exhibitors. The conference was packed with talks about how the industry is girding for the explosive data growth expected to be driven by IoT and 5G cellular. Another key indicator of growing momentum was a 30% increase in attendance of conference short courses meant to educate professionals on the technical aspects of photonics.
The real buzz however, came with several noteworthy news items in March. Among them was a press release by Luxtera where they announced they will be offering a high performance silicon photonics platform with TSMC. The new platform will enable system-on-chip integration of optical interconnect with CMOS logic and will be leverage TSMC’s 7nm CMOS technology. The Luxtera platform is targeting next-generation silicon photonics solutions to deliver 100G-per-lane optical interconnects, starting with 100GBase-DR and 400GBase-DR4 transceivers which they anticipate launching in 2018.
This was promptly followed by a press release from TowerJazz where they too announced they will be providing a new Silicon Photonics process targeting the Optical Transceiver Electronics market. The TowerJazz SiPho process will be based on their SiGe BiCMOS process. When you start seeing production foundries like TSMC, TowerJazz and GLOBAL FOUNDRIES (as announced late last year) getting into the market you know the significant volumes are on their way. This is big!
And lastly, of note was an offer was made by IDT to purchase GigPeak for $250M. GigPeak offers optical interfaces for communications, data centers and military and avionic modules. GigPeak had record profits for its fourth quarter and fiscal 2016 with shipments of its 40 Gbps QSFP+ and 100Gbps QSFP28 ICs for active optical cables (AOCs) and optical transceiver modules into data center customers. The company is also currently sampling driver and trans-impedance amplifier (TIA) ICs for 200 Gbit/s short-reach and long-reach PAM4 Ethernet applications.
The second week of my travels was spent on the east coast of the U.S. traveling up and down the I-90 corridor. One of the most interesting observations of that week was the uptake in the number of integrated photonics projects coming from commercial companies versus past activity which was primarily driven by universities and R&D labs. This was echoed by Twan Korthorst, CEO of PhoeniX Software, where he presented a graph at the PIC International Conference showing a shift of new PhoeniX users coming from commercial companies as opposed to academia. On a side note, PhoeniX’s OptoDesigner tool won the EPIC Award at this year’s PIC International show in the design and test category. While good news for PhoeniX, the interesting part for the reader is that more than 6000 engineers cast ballots for this award. That’s a lot of people for a nascent industry. It also explains PhoeniX’s 45% CAGR for PIC tools over the last four years.
The final week of my travels was spent in Boston at the MIT campus where I attended an AIM Photonics sponsored meetings to road map requirements for the integrated photonics ecosystem. In many cases members were excited to see road map items being accelerated forward by industry.
One of the most interesting presentations was given by Microsoft where they presented on their integrated photonics work used in Time-of-Flight (ToF) cameras and sensors. These cameras give full 3D imaging information for applications such as facial recognition security features. ToF sensors are already in the iPhone 7 and could be applied to future laptops, phones, TVs and gaming consoles. Cameras with 3D depth capabilities can be applied to a wide variety of applications such as gaming, in-air gesturing and augmented reality.
Microsoft, Apple, Intel and Google are all working to bring this ToF technology to bear. Now that would represent some real volume.
This is just the beginning as engineers are barely scratching the surface of what can be done with integrated photonics. From long haul telecommunications, RF and microwave applications, WIFI networks and data center switches, to high volume applications in automotive, mobile devices, industrial sensing and medical and bio-sensing arenas, it’s time to start placing your bets. Hang on to your hats. It’s going to be a wild ride for the next decade!
See also:
– Luxtera and TSMC Collaborate on NexGen Silicon Photonics
– TowerJazz Announces Silicon Photonics Offering
– IDT Makes Offer on GigPeak
– PhoeniX Software Selected for PIC Design & Test Award
Shootout at 22nm!
For an industry that drives improvement at an exponential rate it is funny how often something old is new again. Intel went into high volume production on 22nm in 2011, and TSMC and Samsung have both had 20nm technologies in production for several years. And yet, recently we have seen renewed interest in 22nm. GLOBALFOUNDRIES has a 22nm FDSOI technology (22FDX) ramping now, at their recent technology forum TSMC announced a bulk 22nm technology 22ULP for 2017 production and this week Intel also announced a new 22nm FinFET technology 22FFL or 2017 production. Why the resurgence of interest in 22nm?
20nm/22nm is the last node where the industry primarily relied on planar bulk technology and is also the break point where multi-patterning starts to come in. At smaller dimensions’ leakage issues have driven the transition to fully depleted devices with FinFETs leading the way. FinFETs provide excellent drive current and a good scaling path with 16nm/14nm processes in high volume production, 10nm ramping and 7nm on the horizon. With each new node, the cost to manufacture a transistor has come down and Moore’s law has continued, but this has come at a high price. Design rules have been growing rapidly and the cost to design on these processes is so high that only the largest volume products can justify the necessary investment in development costs. With each new node, fewer products will be designed onto each new technology. One of the key emerging areas for the industry is IOT where the opportunity space is expected to be split between many lower volume products. The need for processes with lower design costs is obvious. IOT we will also need very low power, RF, analog and reasonable digital density. All of the three companies mentioned above are targeting this market with these new 22nm processes.
The key 22nm process objectives are low design cost, little or no multi-patterning, low power and the features needed for IOT and mobile.
GLOBALFOUNDRIES (GF) 22FDX
I have written about 22FDX previously here and here. 22FDX is based on fully depleted SOI (FDSOI) and offers the unique ability to use biasing to achieve multiple threshold voltages and dynamically scale performance. 22FDX offers the lowest operating voltage of any process I am aware of at 0.4 volts. Since power consumption is proportional to voltage squared, 22FDX should provide very low power operation. 22FDX offers 50% faster speed or 18% lower power than GLOBALFOUNDRIES 28nm process. 22FDX also offers excellent RF performance with NMOS FT/FMAX of 350/325GHz and PMOS FT/FMAX of 290/250GHz. This is likely far higher than either of the other 22nm processes, for example GF 14LPP FinFET process only achieves FMAX of ~150GHz. 22FDX is ramping up now.
TSMC 22ULP
Announced only a few weeks ago, 22ULP is due to ramp by the end of 2017. 22ULP is based on a bulk technology and TSMC claims the Ion/Ioff curve is identical to a “22nm FDSOI” technology. The operating voltage is 0.6 volts and the process is said to offer 15% higher performance or 35% lower leakage than TSMC’s 28nm process.
Intel 22FFL
Announced this week, 22FFL is due to ramp in Q4 of 2017. 22FFL is based on Intel’s 22nm FinFET process that has been in production since 2011. 22FFL offers HP transistor with performance similar to Intel’s 14++ process and low leakage transistors with >100x lower leakage, see figure 1. RF is supported although FinFET RF performance is likely not nearly as good as FDSOI due to higher parasitic capacitances.
Figure 1. 22FFL Performance.
Process comparison
All three company’s processes are targeted at lower design costs and meeting the needs of IOT types of applications. Table 1 compares some of the key process characteristics for the three processes.
border=”1″ align=”center”
|-
| style=”width: 156px” | Company
| style=”width: 65px; text-align: center” | GF
| style=”width: 66px; text-align: center” | TSMC
| style=”width: 60px; text-align: center” | Intel
|-
| style=”width: 156px” | Process name
| style=”width: 65px; text-align: center” | 22FDX
| style=”width: 66px; text-align: center” | 22ULP
| style=”width: 60px; text-align: center” | 22FFL
|-
| style=”width: 156px” | Process type
| style=”width: 65px; text-align: center” | FDSOI
| style=”width: 66px; text-align: center” | Bulk
| style=”width: 60px; text-align: center” | FinFET
|-
| style=”width: 156px” | CPP (nm)
| style=”width: 65px; text-align: center” | 90 est
| style=”width: 66px; text-align: center” | 105 est
| style=”width: 60px; text-align: center” | 108
|-
| style=”width: 156px” | MMP (nm)
| style=”width: 65px; text-align: center” | 78 est
| style=”width: 66px; text-align: center” | 80 est
| style=”width: 60px; text-align: center” | 90
|-
| style=”width: 156px” | Tracks
| style=”width: 65px; text-align: center” | 8
| style=”width: 66px; text-align: center” | 7
| style=”width: 60px; text-align: center” | 7
|-
| style=”width: 156px” | CPP x MMP x Track (nm2)
| style=”width: 65px; text-align: center” | 56,160
| style=”width: 66px; text-align: center” | 58,800
| style=”width: 60px; text-align: center” | 68,040
|-
| style=”width: 156px” | Vdd (volts)
| style=”width: 65px; text-align: center” | 0.4
| style=”width: 66px; text-align: center” | 0.6
| style=”width: 60px; text-align: center” | NA
|-
Table 1. Process comparison
Looking at the three processes the GF 22FDX process appears to likely have the densest logic (although we do not have exact numbers for GF and TSMC). 22FDX use 2 multi-patterning layers in the middle of line to drive tighter interconnect plus has the smallest projected contacted poly pitch. 22FDX will also likely have the best RF performance and active power consumption. On other performance and leakage metrics we don’t have enough data to draw any conclusions yet.
One critical factor in designing for any technology is the availability of IP. With TSMC’s 22ULP being a planar bulk shrink from 28nm they will likely have the richest IP offering providing the fastest deign path. At their manufacturing day Intel had a foundry panel including executives from Cadence, ARM and Synopsys and they are clearly working on that area but likely still playing catch up. I know GF is also putting a lot of emphasis on IP and the design environment but it isn’t clear to me how much traction they are getting.
Conclusion
Designers of IOT and other mobile devices now have three new 22nm processes to choose from. The three processes take very different approaches. GF’s 22FDX is the most radical departure from the main stream but also likely delivers the best density, RF and power performance. TSMC’s 22ULP bulk planar process can likely offer the richest IP environment. Intel’s 22FFL is an evolution of the 22GP process that is one of the highest yielding processes in Intel’s history and offers 14++ like performance with very low leakage transistors.
Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!
Yesterday I attended Intel’s manufacturing day. This was the first manufacturing day Intel has held in three years and according to Intel their most in depth ever.
Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers – GLOBALFOUNDRIES, Intel, Samsung and TSMC. Comparing logic technologies to each other requires a metric for process density.
Continue reading “Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!”
Top 10 Updates from the TSMC Technology Symposium, Part II
An earlier article described some of the technical and business highlights from the recent TSMC Symposium in Santa Clara (link). This article continues that discussion, with the top five updates.
Continue reading “Top 10 Updates from the TSMC Technology Symposium, Part II”
Top 10 Updates from the TSMC Technology Symposium, Part I
Last week, TSMC held their 23rd annual technical symposium in Santa Clara. In the Fall, TSMC conducts the OIP updates from EDA/IP partners and customers. The theme of the Spring symposium is solely on TSMC’s technology development status and the future roadmap. Indirectly, the presentations also provide insight into the electronics industry as a whole, based upon the market segments where TSMC is focusing, with their R&D investments.
Continue reading “Top 10 Updates from the TSMC Technology Symposium, Part I”
TSMC Talks About 22nm, 12nm, and 7nm EUV!
The TSMC Symposium was jam-packed this year with both people and information. I had another 60 minutes of fame in the Solido booth where I signed 100 books, thank you to all who stopped by for a free book and a SemiWiki pen. SemiWiki bloggers Tom Dillinger and Tom Simon were also there so look for more TSMC Symposium blogs coming in the next few days. If you have specific questions ask them here and I will make sure you get answers.
Rick Cassidy, President, TSMC North America again kicked of the conference with a nice overview of the semiconductor business. In fact, TSMC shipped 5.8M (12” equiv) wafers in 2016 to more than 450 customers with 5,238 products. Approximately 71% of the resulting revenue went through Rick and the TSMC North American organization so congratulations to them on a job well done.
One of the reoccurring points made by Rick and the other TSMC executives is that TSMC does not compete with their customers which is the foundation of the pure-play foundry business and the key to the success of the fabless semiconductor industry, absolutely.
This year TSMC really focused on custom process platforms for key market segments of the semiconductor industry. I went into a bit more detail on this in my pre-symposium blog TSMC Design Platforms Driving Next-Gen Applications. That blog went viral with more than 10,000 views in one week so you may want to check it out.
There were three big announcements yesterday in my opinion:
1. 22nm ULP
2. 12nm FFC
3. 7nm EUV
Most of us had advanced knowledge of this but it was nice to hear more details in front of more than 1,000 TSMC customers. Again, this is an invitation only event with no recording or photography allowed so much more information is made available than open events or conferences.
TSMC formally introduced 22nm ULP (an optimized version of 28nm HPC+) and 12nm FFC (an optimized version of 16nm). 22nm ULP offers a 10% area reduction and either a 15% performance gain over 28nm or a 35% power reduction. TSMC also has 55nm ULP, 40nm ULP, and 28nm ULP all targeted at IoT and other low power and low cost applications. 12nm FFC offers a 10% performance gain or a 25% power reduction. 12nm also offers a 20% area reduction with 6T Libraries versus 7.5T or 9T.
TSMC 10nm is now fully qualified and in HVM at Giga Fabs 12 and 15. TSMC is scheduled to ship 400,000 wafers in 2017 so you can expect the next Apple iProducts to sport TSMC 10nm SoCs, definitely.
Other than that, 10nm was not discussed much because it is another short node like 20nm. Remember, TSMC introduced double patterning at 20nm then quickly followed with FinFETs at 16nm. This proved to be very a wise approach since the same fabs were used for both 20nm and 16nm which simplified the 16nm ramp. We will see the same with 10nm and 7nm. TSMC ramped 10nm without quad patterning and will add it with 7nm, again using the same fabs.
7nm was the focus of the technical discussions of course because it represents several firsts for our industry. 7nm will also represent the biggest market share for TSMC for one node, second being 28nm I believe. It would be easier to count the big semiconductor companies that are NOT using TSMC 7nm and the only two I can think of are Samsung and Intel.
In comparison to 16FF+, TSMC 7nm is said to offer a 3.3x density, 30% speed, and a 60% power improvement. TSMC will again offer multiple versions of 7nm for platform specific applications (Mobile, IoT, AI, and Automotive). The 7nm SRAM bit cell is .37x compared to 16nm which I believe will be the smallest SRAM bit cell in production so congratulations to the SRAM team in Hsinchu. 7nm will hit risk production in April and HVM in the first half of 2018, and yes, next year’s iProducts will sport TSMC 7nm SoCs.
The big shocker to me was that TSMC is still committed to introducing EUV at 7nm in 2019. Based on what I saw at the SPIE conference last month EUV would miss 7nm completely. This will be another first for the industry (EUV in production) so I can see the incentive but I highly doubt the ROI will be there at 7nm.
TSMC also stated that 5nm development is progressing according to plan with good SRAM yield. TSMC is still scheduling 5nm for 2020 but they did not say at what level EUV would be used. Probably because it depends on the EUV success at 7nm.
Also read: Top 10 Updates from the TSMC Technology Symposium, Part I
TSMC Design Platforms Driving Next-Gen Applications
Coming up is the 23rd annual TSMC Technology Symposium where you can get first-hand updates on advanced and specialty technologies, advanced backend capabilities, future development plans, and network with hundreds of TSMC’s customers and partners. This year the Silicon Valley event kicks off at the Santa Clara Convention Center. For more information the Symposium landing page is HERE but first lets talk about design platforms.
The semiconductor design ecosystem, semiconductor companies, and TSMC are uniting around new methods to overcome chip design challenges by integrating the right tools and technologies into customized, powerful design platforms.
It is becoming apparent that the next growth driver for the IC industry is “ubiquitous computing” where data is generated, collected, filtered, processed and analyzed not just in the cloud or network, but also locally in smart devices all around us. To help its customers seize these opportunities, TSMC and its Open Innovation Platform® partners have developed four application-specific platforms for the next generation of high-growth applications: Mobile, High-Performance Computing (HPC), Automotive, and Internet of Things.
Smartphones occupied much of the last decade’s engineering resources and continue to grow at a healthy clip – Gartner reports 1.5 billion units sold in 2016 – pushing advanced semiconductor technology and design to new heights. However, it is now clear that mobile was just the beginning of a new silicon revolution as industry focus rapidly shifts to the optimization of advanced technology for automotive, HPC and IoT.
In mobile, growth in silicon content per device is driven by features such as dual camera, fingerprint sensors, AR/VR and migration to 4G, 4G+ and 5G. For HPC, artificial intelligence and deep learning will have significant impacts on many industries including healthcare, media and consumer electronics. On the automotive front, ADAS, night-vision, and smart energy for hybrid and electric vehicles promise to make driving more convenient, safe and green. Finally, IoT opens up a multitude of opportunities for ICs that will transform the way we live and improve how societies can be organized and managed through improved efficiency and pervasive communication.
Dr. Cliff Hou, TSMC Vice President of Research & Development, Design and Technology Platform, has pioneered the evolution of design ecosystems to design platforms and the application-specific design enablement that addresses distinct product requirements of each of these four segments. Dr. Hou asserts that application-specific design platforms deliver greatly enhanced solutions that simplify highly complex design activity, reducing the time and effort needed to bring products to market for these high-growth opportunities.
Each TSMC process and packaging optimized design platform includes reference subsystem designs to facilitate innovation; processor cores (CPU, GPU); standard interfaces, Analog/Mixed Signal IP; foundation IP that includes standard cells, SRAM and I/O; design flow, design guideline and EDA tools; and PDK and Tech Files. The goals and readiness of each platform is summarized below:
If you were lucky enough to get a golden ticket to this event it would be a pleasure to meet you. SemiWiki bloggers Tom Dillinger, Tom Simon, and myself will be there blogging live and I will be giving away signed copies of our book on The History of ARM “Mobile Unleashed” in the Solido booth during the lunch break. If you would like to do a meet and greet and get a free book stop on by and say hello.
About TSMC
TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 470 customers and manufactured more than 8,900 products for various applications covering a variety of computer, communications and consumer electronics market segments. Total capacity of the manufacturing facilities managed by TSMC, including subsidiaries and joint ventures, reached above 9 million 12-inch equivalent wafers in 2015. TSMC operates three advanced 12-inch wafer GIGAFAB™ facilities (fab 12, 14 and 15), four eight-inch wafer fabs (fab 3, 5, 6, and 8), one six-inch wafer fab (fab 2) and two backend fabs (advanced backend fab 1 and 2). TSMC also manages two eight-inch fabs at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company Limited, In addition, TSMC obtains 8-inch wafer capacity from other companies in which the Company has an equity interest.
TSMC’s 2015 total sales revenue reached a new high at US$26.61 billion. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea.
EUV is NOT Ready for 7nm!
The annual SPIE Advanced Lithography Conference kicked off last night with vendor sponsored networking events and such. SPIE is the international society for optics and photonics but this year SPIE Advanced Lithography is all about the highly anticipated EUV technology. Scotten Jones and I are at SPIE so expect more detailed blogs on the keynotes and sessions this week.
Attend SPIE Advanced Lithography
Come to the world’s premier lithography event. For over 40 years, SPIE has brought together industry leaders to solve the latest challenges in lithography and patterning in the semiconductor industry. Check out the 2017 News & Photo page andStay on top of what is happening before, during, and after the 2017 SPIE Advanced Lithography meeting in San Jose.
The many BILLION dollar question of course is: When will EUV be ready for high volume manufacturing?
According to Intel EUV Manager Dr. Britt Turkot, at this point in time, EUV is not ready for HVM and may not be ready for 7nm. Britt has been with Intel for 20+ years and is a regular presenter at SPIE. In fact, Britt did a similar presentation last year which was nicely summarized by Scotten Jones: TSMC and Intel on the Long Road to EUV, by Scotten Jones, Published on 02-23-2016 05:00 AM. You can get a full list of Scotten’s blogs HERE.
If you look point-for-point, according to Britt, not much has changed. As Scotten pointed out, three years ago the key issues were: Photoresist – line width roughness (LWR) and outgassin, Tools – source power and availability, and Reticle – killer defects and pellicles.
Photoresist technology continues to improve but no breakthroughs have been reported.
The current power roadmap is to have 250 watts in the 2016-2017 timeframe, >250 watts in the 2018-2019 timeframe. From what I have heard thus far, power in the field is closer to 100 watts than 200 so we still have a ways to go before HVM.
One of the most interesting points was particles and pellicles. According to Britt, particles are a much bigger problem than ASML has disclosed so pellicles will be required. I’m sure we will hear more about this during the conference but pellicles are a double edge sword. They do reduce the number of wafer defects caused by particles but they also draw source power which is already a key issue for throughput and machine availability.
EUV photomask inspection was also discussed. Intel has been pushing for an actinic based inspection tool and that push continues. The question of course is: Who is going to pay for it? My guess is that, as with most semiconductor manufacturing roadblocks, there will be an inspection workaround to get EUV into production before R&D dollars are spent on actinic.
As we already know TSMC has skipped EUV for 7nm but is planning on exercising EUV at 7nm in preparation for EUV at 5nm. At last year’s SPIE, Intel, Samsung, and GLOBALFOUNDRIES still had EUV planned for 7nm but we have heard some waffling on the subject. It will be interesting to get another EUV update on 7nm and 5nm from the people who are actually using it.
Later today Intel will again keynote SPIE and present “EUV readiness for HVM” and Samsung will again present “Progress in EUV Lithography toward manufacturing”. Scotten will do thorough blogs on the conference as he has in the past. You can read Scotten’s very technical event related blogsHERE. If you are attending SPIE it would be a pleasure to meet you, absolutely.
Also read:An Steegen ISS Talk and Interview – Patterning Options for Advanced Nodes
SPIE Advanced Lithography and Synopsys!
SPIE is the premier event for lithography held in Silicon Valley and again Scotten Jones and I will be attending. EUV is generally the star of the show and this year will be no different now that TSMC has committed to EUV production in 2019.
Last year at SPIE, TSMC presented the history of EUV development from the beginning in 1985 as Soft X-Ray to the name change to EUV in 1993. TSMC forecasted that they will “exercise” EUV at 7nm and will introduce EUV for production use at 5nm. TSMC now says they will in fact insert EUV into 7nm in the second year of production (2019) in preparation for EUV at 5nm in 2020. So finally we will have EUV in production after more than 30 years of R&D and so many false starts!!!!!
This year Intel will again keynote SPIE and present “EUV readiness for HVM” and Samsung will again present “Progress in EUV Lithography toward manufacturing”. Scott will do thorough blogs on the conference as he has in the past. You can read Scott’s very technical event related blogs HERE. If you are attending SPIE it would be a pleasure to meet you, absolutely.
A new event at this year’s SPIE is the Synopsys Technical Forum where you will learn the latest on Synopsys Manufacturing’s mask synthesis, mask data prep and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have addressed the challenges of 10nm and 7nm.
Overview
Synopsys provides industry-proven EDA solutions to meet the demands of today’s advanced IC manufacturing processes while setting the standard in platform flexibility to enable innovative and custom solutions for next-generation technology nodes. Synopsys’ comprehensive Mask Synthesis, Mask Data Preparation, TCAD, and Yield Management tools provide leading edge performance, accuracy, quality, and cost of ownership for all your production and development needs.
Synopsys Technical Forum Agenda
[TABLE] cellpadding=”5″ style=”width: 100%”
|-
| align=”center” valign=”top” | Time
| valign=”top” style=”width: 400px” | Presentation Title
| align=”center” valign=”top” | Speaker
| align=”center” valign=”top” | Company
|-
| valign=”top” | 12:30
| colspan=”3″ valign=”top” | Registration & Lunch
|-
| valign=”top” | 1:00
| valign=”top” | Welcome & Introduction
| align=”center” valign=”top” | Howard Ko
| valign=”top” | Synopsys
|-
| valign=”top” | 1:30
| valign=”top” | DTCO Metrics for Patterning Design Arc Definition at 7nm and Beyond
| align=”center” valign=”top” | Derren Dunn, Ph.D.
| valign=”top” | IBM
|-
| valign=”top” | 2:10
| colspan=”3″ valign=”top” | Break & Prize Drawing #1
|-
| valign=”top” | 2:25
| valign=”top” | ILT Optimization of EUV Masks for Sub – 7nm Lithography
| align=”center” valign=”top” | Kevin Lucas
| valign=”top” | Synopsys
|-
| valign=”top” | 3:05
| valign=”top” | Keynote: Advanced Patterning and Litho Options for Challenging Geometries
| align=”center” valign=”top” | Hyunjo Yang
| valign=”top” | SKHynix
|-
| valign=”top” | 3:50
| colspan=”3″ valign=”top” | Thank You & Drawing #2
|-
Visit Synopsys at Booth #206
Tuesday, February 28: 10:00 a.m. to 5:00 p.m.
Wednesday, March 1: 10:00 a.m. to 4:00 p.m.
Location
San Jose Convention Center
Directions
Synopsys Technical Program
Security applications for direct-write lithography(Keynote Presentation)
Mike Borza, Synopsys Inc. (Canada) [10144-3]
Correlation of experimentally measured atomic scale properties of EUV photoresist to modeling performance: an exploration
Yudhishthir Kandel, Synopsys, Inc. (USA); Jonathan Chandonait, SUNY Polytechnic Institute (USA); Sajan Marokkey, Lawrence S. Melvin III, Qiliang Yan, Benjamin D. Painter, Synopsys, Inc. (USA); Gregory H. Denbeaux, SUNY Polytechnic Institute (USA) [10143-7]
Modeling EUVL patterning variability for metal layers in 5nm technology node and its effect on electrical resistance
Weimin Gao, Synopsys GmbH (Belgium); Lawrence S. Melvin III, Synopsys, Inc. (USA); Itaru Kamohara, Synopsys GmbH (Germany); Vicky Philipsen, Vincent Wiaux, Eric Hendrickx, Ryoung-Han Kim, IMEC (Belgium)[10143-14]
Advanced fast 3D DSA model development and calibration for design technology cooptimization
Kafai Lai, IBM Thomas J. Watson Research Ctr. (USA); Balint Meliorisz, Thomas Mülders, Hans-Jürgen Stock, Synopsys GmbH (Germany); Sajan Marokkey, Synopsys, Inc. (USA); Wolfgang Demmerle, Synopsys GmbH (Germany); Chi-Chun Liu, Cheng Chi, Jing Guo, Albany NanoTech (USA)[10144-16]
Experimental characterization of NTD resist shrinkage
Bernd Küchler, Thomas Mülders, Synopsys GmbH (Germany); Hironobu Taoka, Nihon Synopsys G.K. (Japan); Weimin Gao, Synopsys NV (Germany); Ulrich Klostermann, Synopsys GmbH (Germany); Sou Kamimura, FUJIFILM Corp. (Japan); Grozdan Grozev, FUJIFILM Corp. (Belgium); Masahiro Yoshidome, Michihiro Shirakawa, FUJIFILM Corp. (Japan); Waikin Li, IMEC (Belgium)[10147-14]
Modeling of NTD resist shrinkage
Thomas Mülders, Hans-Jürgen Stock, Bernd Küchler, Ulrich Klostermann, Wolfgang Demmerle, Synopsys GmbH (Germany)[10146-21]
Source defect impact on pattern shift
Artak Isoyan, Chander Sawh, Lawrence S. Melvin III, Synopsys, Inc. (USA) [10147-21]
Cost effective solution using inverse lithography OPC for DRAM random contact layer
Jinhyuck Jeon, Jae-Hee Hwang, Jaeseung Choi, Seyoung Oh, Chan-Ha Park, Hyun-Jo Yang, SK Hynix, Inc. (Korea, Republic of); Thuc Dam, Synopsys, Inc. (USA); Munhoe Do, Dongchan Lee, Synopsys Korea Inc. (Korea, Republic of); Guangming Xiao, Jung-Hoe Choi, Kevin Lucas, Synopsys, Inc. (USA)[10148-8]
Resist 3D aware mask solution with ILT for resist failure hotspot repair
Guangming Xiao, Kosta S. Selinidis, Kevin Hooker, Synopsys, Inc. (USA); Wolfgang Hoppe, Synopsys, Inc. (Germany); Thuc Dam, Kevin Lucas, Synopsys, Inc. (USA)[10147-25]
New methodologies for lower-K1 EUV OPC and RET optimization
Kevin Hooker, Yunqiang Zhang, Kevin Lucas, Aram Kazarian, Joshua P. Tuttle, Guangming Xiao, Synopsys, Inc. (USA)[10143-45]
Exposure source error and model source error impact on optical proximity correction
Lawrence S. Melvin III, Artak Isoyan, Chander Sawh, Synopsys, Inc. (USA)[10147-32]
Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond (Invited Paper)
Derren N. Dunn, IBM Research (United States); John R. Sporre, Univ. of Illinois at Urbana-Champaign (United States); Ronald Gull, Synopsys Switzerland, LLC (Switzerland); Peter Ventzek, Tokyo Electron America, Inc. (United States); Alok Ranjan, TEL Technology Ctr., America, LLC (United States) [10149-36]
Synopsys Posters
Compact modeling for the negative tone development processes
Lawrence S. Melvin III, Synopsys, Inc. (USA); Chun-Chieh Kuo, Synopsys, Inc. (Taiwan); Jensheng H. Huang, Synopsys, Inc. (USA)[10147-63]
Addressing optical proximity correction (OPC) challenges from highly nonlinear OPC models
Stephen Jang, Synopsys, Inc. (USA) [10147-64]
Stitching-aware in-design DPT auto fixing for sub-20nm logic devices
Soo Han Choi, David Pemberton-Smith, Sai Krishna K.V.V.S, Synopsys, Inc. (USA)[10148-46]
Using pattern matching to increase performance in hotspot fixing flows
Bradley J. Falch, Synopsys, Inc. (USA) [10148-49]