TSMC – Page 2 – SemiWiki

October 8, 2024July 17, 2025

Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024

Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024
by Kalar Rajendiran on 10-08-2024 at 10:00 am
Categories: 3D IC, AI, Analytics, Chiplet, EDA, Foundries, IP, TSMC

3DFabric Silicon Validated Thermal Analysis

At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the design process for these cutting-edge solutions has been critical, and 3DBlox is central to this mission. 3DBlox is an innovative framework inclusive of a standardized design language, introduced by TSMC aimed at addressing the complexities of 3D integrated circuit (3DIC) design. The following is a synthesis of that talk, delivered by Jim Chang, Deputy Director at TSMC for the 3DIC Methodology Group.

Progress from 2022 to 2023: Laying the Foundations for 3DBlox

In 2022, TSMC began exploring how to represent their 3DFabric offerings, particularly CoWoS (Chip-on-Wafer-on-Substrate) and INFO (Integrated Fan-Out), which are critical technologies for 3DIC. CoWoS integrates chips using a silicon interposer, while INFO uses RDL (Redistribution Layer) interposers. TSMC combined these approaches to create CoWoS-R, replacing the silicon interposer with RDL technology, and CoWoS-L, which integrates local silicon interconnects.

With these building blocks in place, TSMC realized that they needed a systematic way to represent their increasingly complex technology offerings. This led to the creation of 3DBlox, which provided a standard structure for representing all possible configurations of TSMC’s 3DFabric technologies. By focusing on three key elements—chiplets, chiplet interfaces, and the connections among interfaces—TSMC was able to efficiently model a wide range of 3DIC configurations.

By 2023, TSMC had honed in on chiplet reuse and design feasibility, introducing a top-down methodology for early design exploration. This methodology allowed TSMC and its customers to conduct early electrical and thermal analysis, even before having all the design details. Through a system that allowed for chiplets to be mirrored, rotated, or flipped while maintaining a master list of chiplet information, TSMC developed a streamlined approach for design rule checking across multiple chiplets.

Innovations in 2024: Conquering Complexity with 3DBlox

By 2024, TSMC faced the growing complexity of 3DIC systems and devised new strategies to address it. The key innovation was breaking down the 3D design challenge into more manageable 2D problems, focusing on the Bus, TSVs (Through-Silicon Vias), and PG (Power/Ground) structures. These elements, once positioned during the 3D floorplanning stage, were transformed into two-dimensional issues, leveraging established 2D design solutions to simplify the overall process.

Key Technology Developments in 2024

TSMC’s focus on maximizing 3DIC design productivity in 2024 revolved around five major areas of development: design planning, implementation, analysis, physical verification, and substrate routing.

Design Planning: Managing Electrical and Physical Constraints

In 3DIC systems, placing the Bus, TSVs, and PG structures requires careful attention to both electrical and physical constraints, especially Electromigration and IR (EMIR) constraints. Power delivery across dies must be precise, with the PG structure sustaining the necessary power while conserving physical resources for other design elements.

One of TSMC’s key innovations was converting individual TSV entities into density values, allowing them to be modeled numerically. By using AI-driven engines like Cadence Cerebrus Intelligent Chip Explorer and Synopsys DSO.ai, TSMC was able to explore the solution space and backward-map the best solutions for bus, TSV, and PG structures. This method allowed designers to choose the best tradeoffs for their specific designs.

Additionally, chip-package co-design was emphasized in 2024. TSMC collaborated with key customers to address the challenges of coordinating between the chip and package teams, which previously operated independently. By utilizing 3DBlox’s common object format and common constraints, teams could collaborate more efficiently, settling design constraints earlier in the process, even before Tech files were available.

Implementation: Enhancing Reuse and Hierarchical Design

As customers pushed for increased chiplet reuse, TSMC developed hierarchical solutions within the 3DBlox language to support growing 3DIC designs. With the increasing number of alignment marks required to align multiple chiplets, TSMC worked closely with EDA partners to identify the four primary types of alignment markers and automate their insertion in the place-and-route flow.

Analysis: Addressing Multi-Physics Interactions

Multi-physics interactions, particularly related to thermal issues, have become more prominent in 3DIC design. TSMC recognized that thermal issues are more pronounced in 3DIC than in traditional 2D designs due to stronger coupling effects between different physical engines. To address this, TSMC developed a common database that allows different engines to interact and converge based on pre-defined criteria, enabling efficient exploration of the design space.

One of the critical analysis tools introduced in 2024 was warpage analysis, crucial as the size of 3DIC fabric grows. TSMC developed the Mech Tech file, defining the necessary information for industry partners to facilitate stress simulation, addressing a gap in warpage solutions within the semiconductor industry.

Physical Verification: Ensuring Integrity in 3DIC Designs

TSMC tackled the antenna effect, a manufacturing issue where metal may accumulate plasma charges that can penetrate gate oxides via TSVs and bumps. By collaborating with EDA partners, TSMC created a design rule checking (DRC) deck that models and captures the antenna effect, ensuring it can be accounted for during the design process.

In 2024, TSMC also introduced enhancements in layout vs. schematic (LVS) verification for 3DIC systems. Previously, LVS decks assumed a one-top-die, one-bottom-die configuration. However, 3DBlox’s new automated generation tools allow for any configuration to be accurately verified, supporting more complex multi-die designs.

Substrate Routing: Tackling the Growing Complexity

As 3DIC integration grows in scale, so does the complexity of substrate routing. Substrate design has traditionally been a manual process. The growing size of substrates, combined with the intricate requirements of modern 3DIC designs, necessitated new innovations in this space.

TSMC’s work on Interposer Substrate Tech file formats began three years ago, and by 2024, they were able to model highly complex structures, such as the inclusion of tear drops in the model. This advancement offers a more accurate and detailed representation of substrates, crucial for the larger and more intricate designs emerging in the 3DIC space. TSMC worked with their OSAT partners through the 3DFabric Alliance to support this format.

Summary: 3DBlox – Paving the Way for 3DIC Innovation

TSMC’s 3DBlox framework has proven to be a crucial step in managing the complexity and scale of 3DIC design. From early exploration and design feasibility in 2023 to breakthroughs in 2024 across design planning, implementation, analysis, physical verification, and substrate routing, TSMC’s innovations are paving the way for more efficient and scalable 3DIC solutions. As the industry moves toward even more advanced 3D integration, the 3DBlox committee announced plans to make the 3DBlox standard publicly available through IEEE. 3DBlox will continue to play a vital role in enabling designers to meet the increasing demands of semiconductor technology for years to come.

Also Read:

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design

TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC OIP Ecosystem Forum Preview 2024

September 26, 2024July 17, 2025

TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC 16th OIP Ecosystem Forum First Thoughts
by Daniel Nenni on 09-26-2024 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

Even though this is the 16^th OIP event please remember that TSMC has been working closely with EDA and IP companies for 20+ years with reference flows and other design enablement and silicon verification activities. The father of OIP officially is Dr. Morris Chang who named it the Grand Alliance. However, Dr. Cliff Hou is the one who actually created the OIP which is now the largest and strongest ecosystem in the history of semiconductors.

I spent a good portion of my career working with EDA and IP companies on foundry partnerships as well as foundries as a customer strategist. In fact, I still do and it is one of the most rewarding experiences of my career. Hsinchu was my second home for many years and the hospitality of the Taiwan people is unmatched. That same hospitality is a big part of the TSMC culture and part of the reason why they are the most trusted technology and capacity provider.

Bottom line: If anyone thinks this 20+ years of customer centric collaboration can be replicated or reproduced, it cannot, the OIP is a moving target, it expands and gets stronger every year. An ecosystem is also driven by the success of the company and in no part of history has TSMC been MORE successful than today, my opinion.

We will be covering the event in more detail next week but I wanted to share my first thoughts starting with a quote from a blog published yesterday by Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC. I met Dan 20 years ago when he was at Chartered Semiconductor. For the last 17 years he has been at TSMC where he started as Deputy Director of the TSMC IP Alliance (working for Cliff Hou) which is now a big part of the TSMC OIP.

Advancing 3D IC Design for AI Innovation by Dan Kochpatcharin

“Our collaboration with TSMC on advanced silicon solutions for our AWS-designed Nitro, Graviton, Trainium, and Inferentia chips enables us to push the boundaries of advanced process and packaging technologies, providing our customers with the best price performance for virtually any workload running on AWS.” – Gary Szilagyi, vice president, Annapurna Labs at AWS

Readers of the SemiWiki Forum will get this inside joke and if you think this quote from AWS is a coincidence you are wrong. C.C. Wei has a very competitive sense of humor!

Dr. L.C. Lu (Vice President of Research & Development / Design & Technology Platform) did the keynote which was quite good. I first met L.C. when he was in charge of the internal TSMC IP group working for Cliff Hou. He is a very smart no nonsense guy who is also a great leader. Coincidentally, L.C. and CC Wei both have P.h.D.s from Yale.

Some of the slides were very similar to the earlier TSMC Symposium slides which tells you that TSMC means what it says and says what it means. There were no schedule changes, it was all about implementation, implementation, and implementation.

L.C. did an interesting update on Design-Technology Co-Optimization (DTCO). I first heard of DTCO in 2022 and it really is the combination of design and process optimization. I do know customers who are using it but this is the first time I have seen actual silicon results. Remember, this is two years in the making for N3 FinFlex.

The numbers L.C. shared were impressive. In order to do real DTCO a foundry has to have both strong customer and EDA support and TSMC has the strongest. For energy efficiency (power savings) N3 customers are seeing 8%-20% power reductions and 6%-38% improvement in logic density depending on the fin configuration.

L.C. also shared DTCO numbers for N2 NanoFlex and the coming A16 SPR (Super Power Rail) which were all in the double digits (11%-30%). I do know quite a few customers who are designing to N2, in fact, it is just about all of TSMC’s N3 customers I am told. It will be interesting to see more customer numbers next year.

L.C. talked about packaging as well which we will cover in another blog but let me tell you this: By the end of 2024 CoWos will have more than 150 tape-outs from more than 25 different companies! And last I heard TSMC CoWos capacity will more than quadruple from 2023 levels by the end of 2026. Packaging is one of the reasons why I feel that the semiconductor industry has never been more exciting than it is today, absolutely!

Also Read:

TSMC OIP Ecosystem Forum Preview 2024

TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC’s Business Update and Launch of a New Strategy

September 19, 2024July 17, 2025

TSMC OIP Ecosystem Forum Preview 2024

TSMC OIP Ecosystem Forum Preview 2024
by Daniel Nenni on 09-19-2024 at 10:00 am
Categories: Events, Foundries, TSMC

The 2024 live conferences have been well attended thus far and there are many more to come. The next big event in Silicon Valley is the TSMC Global OIP Ecosystem Forum on September 25th at the Santa Clara Convention Center. I expect a big crowd filled with both customers and partners.

This is the 16th year of OIP and it has been an honor to be a part of it. The importance of semiconductor ecosystems is greatly understated as is the importance of the TSMC OIP Ecosystem.

The big change I have seen over the last few years is momentum. The FinFET era has gained an incredible amount of ecosystem strength and the foundation of course is TSMC. When we hit 5nm the tide changed in TSMC’s favor with a huge amount of TSMC N5 EDA, IP, and ASIC services support. In fact, there were a record setting number of tape-outs on this node. This momentum has increased at 3nm with TSMC N3 (the final FinFET node) having the strongest ecosystem support and tape-outs in the history of the fabless ecosystem in my experience.

The momentum is continuing with N2 which will be the first GAA node for TSMC. Rumor has it N2 will have comparable tape-outs with N3. It is too soon to say what will happen with the angstrom era but my guess is that semiconductor innovation and Moore’s Law will continue in one form or another.

A final thought on the ecosystem, while it appears that IDM foundries have more R&D strength than pure-play foundries I can assure you that is not the case. The TSMC OIP Ecosystem, for example, includes the largest catalog of silicon verified IP in the history of the semiconductor industry. IP companies first develop IP in partnership with TSMC to leverage the massive TSMC customer base. In comparison, the IDM foundries pay millions of dollars to port select IP to each of their processes to encourage customer demand.

Throughout the FinFET era foundries, customers and partners have spent hundreds of billions of R&D dollars in support of the fabless semiconductor ecosystem which will get the semiconductor industry to the one trillion dollar mark by the end of this decade, absolutely.

Here is the event promo:

Get ready for a transformative event that will spark innovations of today and tomorrow’s semiconductor designs at the 2024 TSMC Global Open Innovation Platform (OIP) Ecosystem Forum!

This year’s forum is set to ignite excitement with a focus on how AI is transforming chip design and the latest advances in 3DIC system design. Join industry trailblazers and TSMC’s ecosystem partners for an inside look at the latest innovations and breakthroughs.

Through a series of compelling, multi-track presentations, you’ll witness firsthand how the ecosystem is collaborating to address critical design challenges and leverage AI in chip design processes.

Engage with thought leaders and innovators at this unique event, available both in-person and online across major global locations, including North America, Japan, Taiwan, China, Europe, and Israel.

Don’t miss out on this opportunity to connect with the forefront of semiconductor technology.

Get the latest on:
• Emerging challenges in advanced node design and corresponding design flows and methodologies for N3, N2, and A16 processes..

• The latest updates on TSMC’s 3DFabric chip stacking and advanced packaging technologies including InFO, CoWoS®, and TSMC-SoIC®, 3DFabric Alliance, and 3Dblox standard, along with innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications.

• Comprehensive design solutions for specialty technologies, enabling ultra-low power, ultra-low voltage, analog migration, RF, mmWave, and automotive designs, targeting 5G, automotive, and IoT applications.

• Ecosystem-specific AI-assisted design flow implementations for enhanced productivity and optimization in 2D and 3D IC design.

• Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.

REGISTER NOW

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TSMC Foundry 2.0 and Intel IDM 2.0

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August 8, 2024August 6, 2024

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
by Fred Chen on 08-08-2024 at 6:00 am
Categories: Lithography, TSMC
1 Comment

At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track cell, this indicates a metal track pitch of 35 nm, while for the 5.5-track cell, the pitch is 38 nm (Figure 1). Just a 3 nm difference in pitch matters a lot for the patterning approach. As will be shown below, choosing the 5.5-track cell for DUV patterning makes a lot of sense.

Figure 1. 210 nm cell height means 38 nm track pitch for 5.5 tracks (left) or 35 nm track pitch for 6 tracks (left).

Extending the 7nm DUV Approach to 5nm

The 5.5-track metal pitch of 38 nm is at the limit of DUV double patterning. It can therefore reuse the same approach used in 7nm, where the 6-track cell metal pitch was 40 nm [3]. This can be as simple as self-aligned double patterning followed by two self-aligned cut blocks, one for each material to be etched (core or gap) (Figure 2). The minimum pitch of the cut blocks (for each material) is 76 nm, allowing a single exposure.

Figure 2. SADP followed by two self-aligned cut blocks (one for the core material, one for the gap material). Process sequence from left to right: (i) SADP (core lithography followed by spacer deposition and etchback, and gapfill; (ii) cut block lithography for exposing gap material to be etched; (iii) refill of cut block for gap material; (iv) cut block lithography for exposing core material to be etched; (v) refill of cut block for core material. Self-aligned vias (not shown) may be partially etched after the block formation [4].

In lieu of SADP, SALELE [5] may be used instead. This would add an extra mask for the gap material, resulting in a total of four mask exposures needed.

Going Below 38 nm Pitch: Hitting the Multipatterning Barrier

For the 3nm node, it is expected that the metal track pitch will go below 30 nm [6]. Any pitch below 38 nm would entail the use of substantially more DUV multipatterning [7]. Yet a comparable amount of multipatterning could also be expected even for EUV, as the minimum pitch from photoelectron spread can be effectively 40-50 nm for a typical EUV resist [8,9]. The edge definition for a 25 nm half-pitch 60 mJ/cm2 exposure is heavily affected by both the photon shot noise and the photoelectron spread (Figure 3).

Figure 3. 25 nm half-pitch electron distribution image exposed with an incident EUV dose of 60 mJ/cm2 (13 mJ/cm2 absorbed), with a 7.5 nm Gaussian blur to represent the electron spread function given in ref. [9]. A 1 nm pixel is used, with 4 secondary electrons per photoelectron.

5nm For All?

The 5.5-track cell provides an easy migration path from 7nm to 5nm using DUV double patterning. Potentially, this is one of the easier ways for Chinese companies to catch up at 5nm, although clearly that would be as far as they can take it.

References

[1] G. Yeap et al., IEDM 2019, Figure 5.

[2] https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

[3] https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/#google_vignette

[4] F. Chen, Self-Aligned Block Redistribution and Expansion for Improving Multipatterning Productivity, https://www.linkedin.com/pulse/self-aligned-block-redistribution-expansion-improving-frederick-chen-rgnwc/

[5] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[6] https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/

[7] F. Chen, Extension of DUV Multipatterning Toward 3nm, https://semiwiki.com/lithography/336182-extension-of-duv-multipatterning-toward-3nm/, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen/

[8] F. Chen, Why NA is Not Relevant to Resolution in EUV Lithography, https://www.linkedin.com/pulse/why-na-relevant-resolution-euv-lithography-frederick-chen-ytnoc, https://semiwiki.com/lithography/344672-why-na-is-not-relevant-to-resolution-in-euv-lithography/

[9] T. Kozawa et al., JVST B 25, 2481 (2007).

Also Read:

Why NA is Not Relevant to Resolution in EUV Lithography

Intel High NA Adoption

Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity

July 22, 2024July 17, 2025

TSMC Foundry 2.0 and Intel IDM 2.0

TSMC Foundry 2.0 and Intel IDM 2.0
by Daniel Nenni on 07-22-2024 at 10:00 am
Categories: 3D IC, Foundries, TSMC
7 Comments

When Intel entered the foundry business with IDM 2.0 I was impressed. Yes, Intel had tried the foundry business before but this time they changed the face of the company with IDM 2.0 and went “all-in” so to speak. The progress has been impressive and today I think Intel is well positioned to capture the NOT TSMC business by providing a trusted alternative to the TSMC leading edge business. The one trillion dollar questions is: Will Intel take business away from TSMC on a competitive basis? I certainly hope so, for the greater good of the semiconductor industry.

On the most recent TSMC investor call, which is the first call with C.C. Wei as Chairman and CEO, TSMC branded their foundry strategy as Foundry 2.0. It is not a change of strategy, it is a new branding based on what TMSC has been successfully doing for years now, adding additional products and services to keep customers engaged. 3D IC packaging is a clear example but certainly not the only one. The Foundry 2.0 brand is well earned and is clearly targeted at Intel IDM 2.0 which I think is funny and a great example of CC Wei’s sharp wit.

I thought for sure that Intel 18A would be the breakout foundry node for Intel but according to the TSMC investor call, that is not the case. TSMC N3 was a runaway hit with 100% of the major design wins. Even Intel used TSMC N3. I hadn’t seen anything like this since TSMC 28nm which was on allocation as a result of being the only viable 28nm HKMG node out of the gate. History repeated itself with N3 due to the delay of 3nm alternatives. This made the TSMC ecosystem the strongest I have ever witnessed with both the domination of N3 and TSMC’s rapidly expanding packaging success. I had originally thought that some customers would stick with N3 until the second generation of N2 appeared but I was wrong. On yesterday’s investor call:

CC Wei: We expect the number of the new tape-outs for 2-nanometer technologies in its first two years to be higher than both 3-nanometer and 5-nanometer in their first two years. N2 will deliver full load performance and power benefit, with 10 to 15 speed improvement at the same power, or 25% to 30% power improvement at the same speed, and more than 15% chip density increase as compared with the N3E.

CC had mentioned this before but I can now confirm this based on my hallway discussions inside the ecosystem at recent conferences: N2 designs are in progress and will start taping out towards the end of this year.

I really don’t think the TSMC ecosystem gets enough credit, especially after the overwhelming success of N3, but the N2 node is a force in itself:

CC Wei: N2 technology development is progressing well, with device performance and yield on track or ahead of plan. N2 is on track for volume production in 2025 with a ramp profile similar to N3. With our strategy of continuous enhancement, we also introduce N2P as an extension of our N2 family. N2P features a further 5% performance at the same power or 5% to 10% power benefit at the same speed on top of N2. N2P will support both smartphone and HPC applications, and volume production is scheduled for the second half of 2026. We also introduce A16 as our next nanosheet-based technology, featuring Super Power Rail, or SPR, as a separate offering.

And, of course, the TSMC freight train continues:

CC Wei: TSMC’s SPR is an innovative, best-in-class backside power delivery solution that is forcing the industry to incorporate another backside contact scheme to preserve gate density and device with flexibility. Compared with N2P, A16 provides a further 8% to 10% speed improvement at the same power, or 15% to 20% power improvement at the same speed, and additional 7% to 10% chip density gain. A16 is best suited for specific HPC products with complex signal routes and dense power delivery network. Volume production is scheduled for the second half of 2026. We believe N2, N2P, A16, and its derivative will further extend our technology leadership position and enable TSMC to capture the growth opportunities way into the future.

Congratulations to TSMC on their continued success, it is well deserved. I also congratulate the Intel Foundry team for making a difference and I hope the 14A foundry node will give the industry a trusted alternative to TSMC out of the starting gate. In my opinion, had it not been for Intel and of course CC Wei’s leadership and response to Intel’s challenge, we as an industry would not be quickly approaching the one trillion dollar revenue mark. Say what you want about Nvidia, but as Jensen Huang openly admits, TSMC and the foundry business is the real hero of the semiconductor industry, absolutely.

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June 28, 2024February 13, 2025

VLSI Technology Symposium – Intel describes i3 process, how does it measure up?

VLSI Technology Symposium – Intel describes i3 process, how does it measure up?
by Scotten Jones on 06-28-2024 at 6:00 am
Categories: Intel Foundry, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
20 Comments

Figure 1. Process Key Dimensions Comparison.

At the VLSI Technology Symposium this week Intel released details on their i3 process. Over the last four nodes Intel has had an interesting process progression. In 2019, 10nm finally entered production with both high performance and high-density standard cells. 10nm went through several iterations eventually resulting in i7, a high-performance cell only process. When we characterize process density, we always talk about the highest density logic standard cell, 10nm achieved just over 100 million transistors per millimeter squared density (MTx/mm²), i7 in in 2022 only achieved approximately 64 MTx/mm² density because it only had high performance cells. i4 entered production in 2023 and is once again a high-performance cell only process and achieves approximately 130 MTx/mm². Finally, i3 will enter production in 2024 on multiple Intel products providing both high performance and high-density cells. The high-density cells achieve approximately 148 MTx/mm² transistor density.

The key dimensions for the processes are compared in figure 1.

Figure 1. Process Key Dimensions Comparison.

In figure 1 the values for 10nm and i7 are actual values measured by TechInsights on production parts, the i4 and i3 values are from the VLSI Technology papers on i4 [1], and i3 [2]. The cell height for i3 of 210nm is for high density cells, there is also a 240nm height high performance cell with the same density as the i4 process. 240nm height high performance cells are 3 fin devices the same at i4 and the 210nm high density cells are 2 fin devices with wide metal zero.

Figure 2 presents the density changes between the processes in graphics form.

From 32nm through 10nm Intel accelerated from 2.0x to 2.4x and then to 2.7x density improvements, but as is the case with other companies pushing the leading edge, i3 is a less than 2x density jump.

Figure 2. Intel Process Density Comparison.

Figure 3 is from the Intel presentation and presents more details on the i4 to i3 process shrink.

Figure 3. i4 to i3 Process Shrink.

The i3 process will offer multiple variants targeted at different applications.

i3 base process and i3-T with TSVs targeted at client, server and base die for chiplet applications.
i3-E offer native 1.2 volt I/O devices, deep N-wells, and long channel analog devices, and is targeted at chipsets and storage applications.
i3-PT targets high performance computing and AI with 9μm pitch TSVs and hybrid bonding.

Figure 4 summarizes the process variants.

Figure 4. i3 Process Variants.

i3 features:

Smaller M2 pitch than i4.
Better fin profile.
Utilizes dipoles to set threshold voltages, i4 does not use dipoles. Dipoles improve gate oxide reliability.
Offer 14, 18, and 21 metal layer options (counts include metal 0).
4 threshold voltages, V:VT, LVT, SVT, HVT.
Contact optimization to provide less overlap capacitance.
More effective EUV usage, i4 was Intel’s first EUV process, i3 EUV processes are less complex.
Lower line resistance and capacitance than i4.
5x lower leakage at the same drive current as i4.
Increased frequency and drive current with no hot carrier increase.
Interconnect delay is now approximately half of overall delay and the base process has better RC delay, the PT process is even better.
At the same power i3 HD cells provide 18% better performance than i4 HP cells.

Figure 5 presents the interconnect pitches for the 14, 18, and 21 metal options.

Figure 5. Interconnect Pitches.

Figure 6 illustrates the improvement in interconnect RC delay.

Figure 6. Interconnect RC Delay.

And finally, figure 7 illustrates the 18% performance improvement over i4.

Figure 7. Interconnect Delay Improvement.

During an analysts briefing session questions and answers session Intel disclosed the channels are all silicon, no silicon germanium channels. Also, i4 designs have been ported to i3 and they are seeing PPA improvements on the same designs.

i3 is currently in high volume manufacturing with multiple Intel products.

i3 clearly represents a significant improvement over i4.

Comparisons to competitors

i3 is a significant improvement over i4 but how does it compare to competitors?

TechInsights has analyzed density, performance, and cost of i3 versus Samsung and TSMC processes. That analysis is available in the TechInsights platform here (free registration required):

Conclusion

Intel’s i3 process is a significant step forward from Intel’s i4 process with better density and performance. Intel’s i3 process is a more competitive foundry process than previous generations. Cost is more in-line with other foundry processes, density is slightly lower than Samsung 3nm and much lower than TSMC 3nm, but it has the best performance of the “3nm” processes.

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June 10, 2024July 17, 2025

TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design

TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
by Mike Gianfagna on 06-10-2024 at 6:00 am
Categories: 3D IC, Events, Foundries, TSMC
2 Comments

The TSMC Technology Symposium provides a worldwide stage for TSMC to showcase its advanced technology impact and the extensive ecosystem that is part of the company’s vast reach. These events occur around the world and the schedule is winding down. TSMC covers many topics at its Technology Symposium, including industry-leading HPC, smartphone, IoT, and automotive platform solutions, 5nm, 4nm, 3nm, 2nm processes, ultra-low power, RF, embedded memory, power management, sensor technologies, and AI enablement. Capacity expansion and green manufacturing achievements were also discussed, along with TSMC’s Open Innovation Platform^®ecosystem. These represent significant achievements for sure. For this post, I’d like to focus on another set of significant achievements in advanced packaging. This work has substantial implications for the future of the semiconductor industry. Let’s examine how TSMC advanced packaging overcomes the complexities of multi-die design.

Why Advanced Packaging is Important

Advanced packaging is a relatively new addition to the pure-play foundry model. It wasn’t all that long ago that packaging was a not-so-glamorous finishing requirement for a chip design that was outsourced to third parties. The design work was done by package engineers who got the final design thrown over the wall to fit into one of the standard package configurations. Today, package engineers are the rock stars of the design team. These folks are involved at the very beginning of the design and apply exotic materials and analysis tools to the project. The project isn’t real until the package engineer signs off that the design can indeed be assembled.

With this part of the design process becoming so critically important (and difficult) it’s no surprise that TSMC and other foundries stepped up to the challenge and made it part of the overall set of services provided. The driver for all this change can be traced back to three words: exponential complexity increase. For many years, exponential complexity increase was delivered by Moore’s Law in the form of larger and larger monolithic chips. Today, it takes more effort and cost to get to the next process node and when you finally get there the improvement isn’t as dramatic as it once was. On top of that, the size of new designs is so huge that it can’t fit on a single chip.

These trends have catalyzed a new era of exponential complexity increase, one that relies on heterogeneous integration of multiple dies (or chiplets) in a single package, and that has created the incredible focus and importance of advanced packaging as critical enabling technology. TSMC summarizes these trends nicely in the diagram below.

TSMC’s Advanced Packaging Technologies

TSMC presented many parts of its strategy to support advanced packaging and open the new era of heterogenous integration. These are the technology building blocks for TSMC’s 3DFabric™ Technology Portfolio:

CoWoS®: Chip-on-Wafer-on-Substrate is a 2.5D wafer-level multi-chip packaging technology that incorporates multiple dies side-by-side on a silicon interposer to achieve better interconnect density and performance. Individual chips are bonded through micro-bumps on a silicon interposer forming a chip-on-wafer (CoW).
InFO: Integrated Fan-Out wafer level packaging is a wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance. The InFO platform offers various package schemes in 2D and 3D that are optimized for specific applications.
TSMC-SoIC®: Is a service platform that provides front-end, 3D inter-chip (3D IC) stacking technologies for re-integration of chiplets partitioned from a system on chip (SoC). The resulting integrated chip outperforms the original SoC in system performance. It also affords the flexibility to integrate additional system functionalities. The platform is fully compatible with CoWoS and InFO, offering a powerful “3Dx3D” system-level solution.

The figure below summarizes how the pieces fit together.

Getting all this to work across the ecosystem requires collaboration. To that end, TSMC has established the 3DFabric Alliance to enable work with 21 industry partners to cover memory, substrate, testing and OSAT collaborations to lower 3DIC design barriers, improve STCO and accelerate 3DIC adoption. The group also drives 3DIC development in tools, flows, IP, and interoperability for the entire 3Dfabric stack. The figure below summarizes the group of organizations that are involved in this work.

There is so much effort going on to support advanced packaging at TSMC. I will conclude with one more example of this work. 3Dblox™ is a standard new language that will help make designing 3D ICs much easier. TSMC created 3Dblox alongside its EDA partners such as Ansys, Cadence, Intel, Siemens, and Synopsys to unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The figure below shows the progress that has been achieved with this effort.

3Dblox Roadmap

To Learn More

I have touched on only some of the great work going on at TSMC to create advanced packaging solutions to pave the way for the next era of multi-die, heterogeneous design. You can get more information about this important effort at TSMC here. And that’s how TSMC advanced packaging overcomes the complexities of multi-die design.

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May 24, 2024November 20, 2024

Ncredible Nvidia

Ncredible Nvidia
by Claus Aasholm on 05-24-2024 at 8:00 am
Categories: AI, Semiconductor Business Intelligence, Semiconductor Services, TSMC
2 Comments

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This article previews Nvidia’s earnings release and will be updated during and after the earnings release. As usual, we will compare and contrast the Nvidia earnings with our supply chain glasses to identify changes and derive insights. Please return to this article, as it will be updated over the next week as we progress with our analysis.

After three insane quarters, Nvidia’s guidance suggests that this quarter will be calmer. I am not sure the stock market can handle growth rates like Nvidia is enjoying once more without going insane. The analysts’ consensus is slightly above Nvidia’s at $24.6B. Our survey shows that the industry expectations are somewhat more optimistic.

From humble beginnings as a graphics company adored by hardcore gamers only, Nvidia is now the undisputed industry champion and has made the industry famous far beyond us wafer nerds.

When people hear you are in the semiconductor industry, they want to know what you think of Nvidia’s stock price (which is insane but could be even more insane). Obviously, this is driven by the irresistible hunger for AI in the data centre, but this is not our expertise (we recommend Michael Spensers: AI Supremacy for that). We will also refrain from commenting on stock prices and concentrate on the business and supply chain side of the story.

The supply chain has already created a frenzy amongst analysts as TSMC reported April Revenue up almost 60%. Our analysis of the TSMC revenue numbers aligned to an April quarter end shows that the TSMC trend is relatively flat and does not reveal much about Nvidia’s numbers. However, TSMC’s revenue numbers do not have to change much for Nvidia’s numbers to skyrocket. The value is not in the silicon right now as we will be diving into later.

The golden goose

The most important market for Nvidia is the data center and its sky-high demand for AI servers. Over the last couple of years, Nvidia and AMD have been chipping away at Intel’s market share until three quarters ago, when Nvidia’s Datacenter business skyrocketed and sucked all value out of the market for the other players. Last quarter Nvidia capture over 87% of all operating profit in the processing market.

This has faced in particular Intel with a nasty dilemma:

Nvidia has eaten Intel’s lunch.

Intel has recently unveiled a bold and promising strategy, a testament to its resilience and determination. However, this strategy comes with significant financial challenges. As illustrated in the comparison below, Intel has historically been able to fund its approximately $4B/qtr Capex as its Operating profits hovered around $11B. But as the market changed, Intel’s operating profit is now approaching zero while its CapEx spending is increasing as a result of the new strategy of also becoming a foundry ased to the area of $6B$/qtr. The increased spending is now approximately $6M and is not a temporary situation but a reality that will persist

Intel can no longer finance its strategy through retained earnings and must engage with the investor community to obtain financing. Intel is no longer the master of its destiny.

Intel is hit by two trends in the Datacenter market:

The transition from CPU to GPU
The transition from Components to Systems.

Not only did Intel miss the GPU transition business, but it also lost the CPU business because of the system transition. Nvidia GPU systems will use their CPUs, Intel is not invited.

The revolution of the semiconductor supply chain

There are two main reasons the AI revolution is changing the data center part of the supply chain.

One is related to the change from standard packaged DRAM to High-Bandwidth Memory (HBM), and the other is related to new packaging technologies (CoWoS by TSMC). Both are related and caused by the need for bandwidth. As the GPU’s computational power increases, it must have faster memory access to deliver the computational advantage needed. The memory needs to be closer to the GPU and more of it, a lot more.

A simplified view of the relevant packaging technologies can be seen below:

The more traditional packaging method (2D) involves mounting the die on a substrate and connecting the pads with bond wires. 2.3D technology can bring the chips closer by flipping them around and mounting them on an interposer (often Silicon).

The current NVIDIA GPUs are made with 2.5D technology. The GPUs are flanked by stacks of DRAM die controlled by a base Memory Logic Die.

3D technology will bring memory to the top of the GPU and introduce many new problems for intelligent semiconductor people to solve.

This new technology is dramatically changing the supply chain. In the traditional model standard of the rest of the industry, the server card manufacturer procured all components from the suppliers individually.

The competition between the Processing, Memory and the Server companies kept pricing in check for the cloud companies.

Much has become more complex in the new AI server supply chain, as seen below.

The processing company is now in control of the supply chain. With Nvidia’s volumes, supply becomes very important, and as all of the technologies and components are leading-edge, the supply can be unstable. Memory companies need dies from foundries and will negotiate and deliver directly to the processing companies. That Nvidia is in control can be seen in their incredible margins.

This change again makes the Semiconductor supply chain more complex, but complexity is our friend.

What did Nvidia report, and what does it mean?

Nvidia posted $26B$ revenue, significantly above guidance and below the $27.5B we believed was the current capacity limit. It looked like Nvidia could squeeze the suppliers to perform at the maximum.

The result was a new record in the Semiconductor industry. Back in ancient history (last year), only Intel and Samsung could break quarterly records, as can be seen below.

Nvidia also disclosed their networking revenue for the first time, through the earlier calls we had a good idea of the size but now it is confirmed.

As we believe almost all of the networking revenue is in the data center category, we expected it to grow as the processing business but networking revenue was down down just under 5% quarterly suggesting the bill of material is shifting in the AI server products.

Even though the networking revenue was down, the growth from same quarter last year was up, making Nvidia the fastest growing networking company in the industry. More about that later.

The most important market for Nvidia is the data center processing market and its rapid uncontrolled disassembly of the old market structure. From being a wholly owned subsidiary of Intel back in 2019, the painful story unfolds below.

In Q1-2024, Nvidia generated more additional processing revenue in the data center than Intel’s total revenue. From an operating profit perspective, Nvidia had an 87% market share and delivered a new record higher than the combined operating profit in Q1-24.

Although Nvidia reported flat networking revenue, the company’s dominance is spreading to Data center networking. Packaging networking into server systems ensures that the networking components are not up for individual negotiation and hurts Nvidia’s networking competitors. It also provides an extraordinary margin.

We have not yet found out what is behind the drop in networking, but it is likely a configuration change in the server systems or a change in categorization inside Nvidia.

Nvidia declared a 10-1 stock split.

Claus Aasholm @siliconomy Spending my time dissecting the state of the semiconductor industry and the semiconductor supply chain. “Your future might be somebody else’s past.”

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May 1, 2024November 20, 2024

Nvidia Sells while Intel Tells

Nvidia Sells while Intel Tells
by Claus Aasholm on 05-01-2024 at 8:00 am
Categories: Semiconductor Business Intelligence, Semiconductor Services, TSMC

AMD’s Q1-2024 financial results are out, prompting us to delve into the Data Center Processing market. This analysis, usually reserved for us Semiconductor aficionados, has taken on a new dimension. The rise of AI products, now the gold standard for semiconductor companies, has sparked a revolution in the industry, making this analysis relevant to all.

Jenson Huang of Nvidia is called the “Taylor Swift of Semiconductors” and just appeared on CBS 60 Minutes. He found time for this between autographing Nvidia AI Systems and suppliers’ memory products.

Lisa Su of AMD, who has turned the company’s fate, is now one of only 26 self-made female billionaires in the US. Later, she was the CEO of the year in Chief Executive Magazine and has been on the cover of Forbes magazine. Lisa Su still needs to be famous in Formula 1

Hock Tan of Broadcom, desperately trying to avoid critical questions about the change of WMware licensing, would rather discuss the company’s strides in AI accelerator products for the Data Center, which has been significant.

An honorable mention goes to Pat Gelsinger of Intel, the former owner of the Data Center processing market. He has relentlessly been in the media and on stage, explaining the new Intel strategy and his faith in the new course. He has been brutally honest about Intel’s problems and the monumental challenges ahead. We deeply respect this refreshing approach but also deal with the facts. The facts do not look good for Intel.

AMD’s reporting

While the AMD result was challenging from a corporate perspective, the Data Center business, the topic of this article, did better than the other divisions.

The gaming division took a significant decline, leaving the Data Center business as the sole division likely to deliver robust growth in the future. As can be seen, the Data Center business delivered a solid operating profit. Still, it was insufficient to take a larger share of the overall profit in the Data Center Processing market. The 500-pound gorilla in the AI jungle is not challenged yet.

The Data Center Processing Market

Nvidia’s Q1 numbers have been known for a while (our method is to allocate all of the quarterly revenue in the quarter of the last fiscal month), together with Broadcom’s, the newest entry into the AI processing market. With Intel and AMD’s results, the Q1 overview of the market can be made:

Despite a lower growth rate in Q1-24, Nvidia kept gaining market share, keeping the other players away from the table. Nvidas’ Data Center Processing market share increased from 66.5% to 73.0% of revenue. In comparison, the share of Operating profit declined from 88.4% to 87.8% as Intel managed to get better operating profits from their declining revenue in Q1-24.

Intel has decided to stop hunting low-margin businesses while AMD and Broadcom maintain reasonable margins.

As good consultants, we are never surprised by any development in our area once presented with numbers. That will not stop us from diving deeper into the Data Center Processing supply chain. This is where all energy in the Semiconductor market is concentrated right now.

The Supply Chain view of the Data Center Processing

A CEO I used to work for used to remind me: “When we discuss facts, we are all equal, but when we start talking about opinions, mine is a hell of a lot bigger than yours.”

Our consultancy is built on a foundation of not just knowing what is happening but also being able to demonstrate it. We believe in fostering discussions around facts rather than imposing our views on customers. Once the facts are established, the strategic starting point becomes apparent, leading to more informed decisions.

“There is nothing more deceptive than an obvious fact.” Sherlock Homes

Our preferred tool of analysis is our Semiconductor Market model, seen below:

The model has several different categories that have proven helpful for our analysis and are described in more detail here:

We use a submodel to investigate the Data Center supply chain. This is also an effective way of presenting our data and insights (the “Rainbow” supply and demand indicators) and adding our interpretations as text. Our interpretations can undoubtedly be challenged, but we are okay with that.

Our current findings that the supply chain is struggling to get sufficient CoWoS packaging technology and High Bandwith Memory is not a controversial view and is shared by most that follow the Semiconductor Industry.

This will not stop us from taking a deeper dive to be able to demonstrate what is going on.

The Rainbow bars between the different elements in the supply chain represent the current status.

The interface between Materials & Foundry shows that the supply is high, while the demand from TSMC and other foundries is relatively low.

Materials situation

This supply/demand situation should create a higher inventory position until the two bars align again in a new equilibrium. The materials inventory index does show elevated inventory, and the materials markets are likely some distance away from recovery.

Semiconductor Tools

The recent results of the semiconductor tools companies show that revenues are going down, and the appetite of IDMs and foundries indicates that the investment alike is saturated. The combined result can be seen below, along with essential semiconductor events:

The tools market has flatlined since the Chips Act was signed, and there can certainly be a causal effect (something we will investigate in a future post). Even though many new factories are under construction, these activities have not yet affected the tools market.

A similar view of the subcategory of logic tools which TSMC uses shows an even more depressed revenue situation. The tools revenue is back to a level of late 2021, in a time with unprecedented expansion of the semiconductor manufacturing foot print:

This situation is confirmed on the demand side as seen in the TSMC Capital Investments chart below.

Right after the Chips Act was signed, TSMC lowered the capex spend to close to half, making life difficult for the tools manufacturers.

The tools foundry interface has high supply and low demand as could be seen in the supply chain model. The tools vendors are not the limiting factor of GPU AI systems.

The Foundry/Fabless interface

To investigate the supply demand situation between TSMC and it’s main customers we choose to select AMD and Nvidia as they have the simplest relationship with TSMC as the bulk of their business is processors made by TSMC.

The inventory situation of the 3 companies can be seen below.

As TSMC’s inventory is building up slightly does not indicate a supply problem however this is TSMC total so their could be other moving parts. The Nvidia peak aligns with the introduction of the H100.

TSMC’s HPC revenue aligns with the Cost of Goods sold of AMD and Nvidia.

As should be expected, these is no surpises in this view. As TSMC’s HPC revenue is growing faster than the COGS of Nvidia and AMD, we can infer that a larger part of revenue is with other customers than Nvidia and AMD. This is a good indication that TSMC is not supply limited from a HPC silicon perspective. Still, the demand is still outstripping supply at the gate of the data centers.

The Memory, IDM interface

That the skyhigh demand for AI systems is supply is limited, can be seen by the wild operating profit Nvidia is enjoying right no. The supply chain of AI processors looks smooth as we saw before. This is confirmed by the TSMC’s passivity in buying new tools. If there was a production bottle neck, TSMC would have taken action from a tools perspective.

An anlysis of Memory production tools hints at the current supply problem.

The memory companies put the brakes on investments right after the last downcycle began. The last two quarters the demand has increased in anticipation of the High Bandwidth Memory needed for AI.

Hynix in their rececent investor call, confirmed that they had been underinvesting and will have to limit standard DRAM manufacturing in order to supply HBM. This is very visible in our Hynix analysis below.

Apart from the limited supply of HBM, there is also a limitation of advanced packaging capacity for AI systems. As this market is still embryonic and developing, we have not yet developed a good data method to be able to analyze it but are working on it.

While our methods does not prove everything, we can bring a lot of color to your strategy discussions should you decide to engage with our data, insights and models.

March 11, 2024July 17, 2025

No! TSMC does not Make 90% of Advanced Silicon

No! TSMC does not Make 90% of Advanced Silicon
by Scotten Jones on 03-11-2024 at 2:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC
26 Comments

Throughout the debate on fab incentives and the Chips Act I keep seeing comments like; TSMC makes >90% of all advanced silicon, or sometimes Taiwan make >90% of all advanced silicon. This kind of ill-defined and grossly inaccurate statement drives me crazy. I just saw someone make that same claim in the SemiWiki forums and I decided it was time to comment on this.

Let’s start with defining what is an advanced semiconductor. Since the specific comment is about TSMC, let’s start with the TSMC definition, TSMC breaks out 7nm and below as advanced. This is a good break point in logic because Samsung and TSMC 7nm both have densities of approximately 100 million transistor per millimeter squared (MTx/mm²). Intel 10nm also has approximately 100 MTx/mm², therefore we can count Samsung and TSMC 7nm and below and Intel 10nm and below.

That all works for logic, but this whole discussion ignores other advanced semiconductors. I would argue that there are three truly leading edge advanced semiconductors in the world today where state-of-the-art equipment is being pushed to the limits of what is achievable: 3DNAND, DRAM, and Logic. In each case there are three or more of the worlds largest semiconductor companies pushing the technology as far and as fast as humanely possible. Yes, the challenges are different, 3DNAND has relatively easy lithography requirements but deposition and etching requirements are absolutely at the edge of what is achievable. DRAM has a mixture of lithography, materials and high aspect ratio challenges. Logic has the most EUV layers and process steps but they are all equally difficult to successfully produce with good yield.

Including 3DNAND and DRAM means we need an “advanced semiconductor” limits for these two processes. When 7nm was first being introduced for logic, 3DNAND was at the 96/92 layer generation and DRAM was at 1y. We will use those as the limits for advanced semiconductors.

In order to complete this analysis without spending man-days that I don’t have to spare, I simply added up the worldwide installed capacity for 3DNAND 96/92L layers and greater, DRAM 1y and smaller and Logic 7nm (i10nm) and smaller. Furthermore I broke out logic into TSMC and other.

Figure 1 illustrates the worldwide installed capacity in percentage broken out by those categories.

Figure 1. Worldwide Advanced Silicon Installed Capacity by Category.

From figure 1 it can be seen that TSMC only represents 12% of worldwide “advanced silicon”, way off the 90% number being thrown around. Now utilization could change these numbers some and I haven’t included that due to time constraints, but I don’t think it would change this that much and as the memory sector recovers it will become a non issue.

I also looked at this a second way which is just worldwide advanced logic, see figure 2.

Figure 2. Worldwide Advanced Logic Installed Capacity by Category.

From figure 2 we can see that even when we look at Advanced Logic TSMC is only 64% versus “90%”.

The only way we would get to 90% is if we defined “advanced silicon” as 3nm logic. This would require a good definition of what 3nm logic is. On a density basis TSMC is the only 3nm logic process in the world, Samsung and Intel are really 5nm processes on a density basis, although Intel i3 is in my estimation the highest performing process available.

In conclusion, TSMC actually only makes up 12% of worldwide Advanced Silicon and only 64% of Advanced Logic. This is not to minimize the importance of TSMC to the global electronics supply chain, but when debating things as important as the worldwide semiconductor supply chain we should at least get the numbers right.

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