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Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024

Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024
by Kalar Rajendiran on 10-08-2024 at 10:00 am
Categories: 3D IC, AI, Analytics, Chiplet, EDA, Foundries, IP, TSMC

3DFabric Silicon Validated Thermal Analysis

At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the design process for these cutting-edge solutions has been critical, and 3DBlox is central to this mission. 3DBlox is an innovative framework inclusive of a standardized design language, introduced by TSMC aimed at addressing the complexities of 3D integrated circuit (3DIC) design.  The following is a synthesis of that talk, delivered by Jim Chang, Deputy Director at TSMC for the 3DIC Methodology Group.

Progress from 2022 to 2023: Laying the Foundations for 3DBlox

In 2022, TSMC began exploring how to represent their 3DFabric offerings, particularly CoWoS (Chip-on-Wafer-on-Substrate) and INFO (Integrated Fan-Out), which are critical technologies for 3DIC. CoWoS integrates chips using a silicon interposer, while INFO uses RDL (Redistribution Layer) interposers. TSMC combined these approaches to create CoWoS-R, replacing the silicon interposer with RDL technology, and CoWoS-L, which integrates local silicon interconnects.

With these building blocks in place, TSMC realized that they needed a systematic way to represent their increasingly complex technology offerings. This led to the creation of 3DBlox, which provided a standard structure for representing all possible configurations of TSMC’s 3DFabric technologies. By focusing on three key elements—chiplets, chiplet interfaces, and the connections among interfaces—TSMC was able to efficiently model a wide range of 3DIC configurations.

By 2023, TSMC had honed in on chiplet reuse and design feasibility, introducing a top-down methodology for early design exploration. This methodology allowed TSMC and its customers to conduct early electrical and thermal analysis, even before having all the design details. Through a system that allowed for chiplets to be mirrored, rotated, or flipped while maintaining a master list of chiplet information, TSMC developed a streamlined approach for design rule checking across multiple chiplets.

Innovations in 2024: Conquering Complexity with 3DBlox

By 2024, TSMC faced the growing complexity of 3DIC systems and devised new strategies to address it. The key innovation was breaking down the 3D design challenge into more manageable 2D problems, focusing on the Bus, TSVs (Through-Silicon Vias), and PG (Power/Ground) structures. These elements, once positioned during the 3D floorplanning stage, were transformed into two-dimensional issues, leveraging established 2D design solutions to simplify the overall process.

Key Technology Developments in 2024

TSMC’s focus on maximizing 3DIC design productivity in 2024 revolved around five major areas of development: design planning, implementation, analysis, physical verification, and substrate routing.

Design Planning: Managing Electrical and Physical Constraints

In 3DIC systems, placing the Bus, TSVs, and PG structures requires careful attention to both electrical and physical constraints, especially Electromigration and IR (EMIR) constraints. Power delivery across dies must be precise, with the PG structure sustaining the necessary power while conserving physical resources for other design elements.

One of TSMC’s key innovations was converting individual TSV entities into density values, allowing them to be modeled numerically. By using AI-driven engines like Cadence Cerebrus Intelligent Chip Explorer and Synopsys DSO.ai, TSMC was able to explore the solution space and backward-map the best solutions for bus, TSV, and PG structures. This method allowed designers to choose the best tradeoffs for their specific designs.

Additionally, chip-package co-design was emphasized in 2024. TSMC collaborated with key customers to address the challenges of coordinating between the chip and package teams, which previously operated independently. By utilizing 3DBlox’s common object format and common constraints, teams could collaborate more efficiently, settling design constraints earlier in the process, even before Tech files were available.

 Implementation: Enhancing Reuse and Hierarchical Design

As customers pushed for increased chiplet reuse, TSMC developed hierarchical solutions within the 3DBlox language to support growing 3DIC designs. With the increasing number of alignment marks required to align multiple chiplets, TSMC worked closely with EDA partners to identify the four primary types of alignment markers and automate their insertion in the place-and-route flow.

Analysis: Addressing Multi-Physics Interactions

Multi-physics interactions, particularly related to thermal issues, have become more prominent in 3DIC design. TSMC recognized that thermal issues are more pronounced in 3DIC than in traditional 2D designs due to stronger coupling effects between different physical engines. To address this, TSMC developed a common database that allows different engines to interact and converge based on pre-defined criteria, enabling efficient exploration of the design space.

One of the critical analysis tools introduced in 2024 was warpage analysis, crucial as the size of 3DIC fabric grows. TSMC developed the Mech Tech file, defining the necessary information for industry partners to facilitate stress simulation, addressing a gap in warpage solutions within the semiconductor industry.

Physical Verification: Ensuring Integrity in 3DIC Designs

TSMC tackled the antenna effect, a manufacturing issue where metal may accumulate plasma charges that can penetrate gate oxides via TSVs and bumps. By collaborating with EDA partners, TSMC created a design rule checking (DRC) deck that models and captures the antenna effect, ensuring it can be accounted for during the design process.

In 2024, TSMC also introduced enhancements in layout vs. schematic (LVS) verification for 3DIC systems. Previously, LVS decks assumed a one-top-die, one-bottom-die configuration. However, 3DBlox’s new automated generation tools allow for any configuration to be accurately verified, supporting more complex multi-die designs.

Substrate Routing: Tackling the Growing Complexity

As 3DIC integration grows in scale, so does the complexity of substrate routing. Substrate design has traditionally been a manual process. The growing size of substrates, combined with the intricate requirements of modern 3DIC designs, necessitated new innovations in this space.

TSMC’s work on Interposer Substrate Tech file formats began three years ago, and by 2024, they were able to model highly complex structures, such as the inclusion of tear drops in the model. This advancement offers a more accurate and detailed representation of substrates, crucial for the larger and more intricate designs emerging in the 3DIC space. TSMC worked with their OSAT partners through the 3DFabric Alliance to support this format.

Summary: 3DBlox – Paving the Way for 3DIC Innovation

TSMC’s 3DBlox framework has proven to be a crucial step in managing the complexity and scale of 3DIC design. From early exploration and design feasibility in 2023 to breakthroughs in 2024 across design planning, implementation, analysis, physical verification, and substrate routing, TSMC’s innovations are paving the way for more efficient and scalable 3DIC solutions. As the industry moves toward even more advanced 3D integration, the 3DBlox committee announced plans to make the 3DBlox standard publicly available through IEEE. 3DBlox will continue to play a vital role in enabling designers to meet the increasing demands of semiconductor technology for years to come.

Also Read:

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design

TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC OIP Ecosystem Forum Preview 2024

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Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design

Synopsys and TSMC Pave the Path for Trillion-Transistor AI and Multi-Die Chip Design
by Kalar Rajendiran on 10-02-2024 at 10:00 am
Categories: 3D IC, AI, Chiplet, EDA, Foundries, IP, Synopsys, TSMC

OIP 2024 Synopsys TSMC

Synopsys made significant announcements during the recent TSMC OIP Ecosystem Forum, showcasing a range of cutting-edge solutions designed to address the growing complexities in semiconductor design. With a strong emphasis on enabling next-generation chip architectures, Synopsys introduced both new technologies and key updates to existing solutions in collaboration with TSMC.

At the heart of this collaboration is the goal of accelerating the development of trillion-transistor chips, which are necessary to support the computational demands of Artificial Intelligence (AI) and high-performance computing (HPC) applications. As these systems continue to grow in complexity, Synopsys and TSMC are collaborating to leverage AI to streamline the design process and ensure power efficiency, scalability, and system reliability. What caught my interest and attention was the focus multi-die, 3D Integrated Circuits (3DICs), and multi-physics design analysis are receiving in this collaboration. Before we dive into that, below is a roundup of the key announcements.

Roundup of the Key Announcements from Synopsys

Synopsys aims to enable the design of more complex, efficient, and scalable multi-die packages that can meet the evolving demands of AI, HPC, and other advanced computing applications.

Synopsys.ai Suite Optimized for TSMC N2 Process Technology: This was a key update, as Synopsys’ AI-driven EDA suite was already known for its ability to improve Quality of Results (QoR). The latest optimization focuses on the N2 process, helping designers move more swiftly to next-generation nodes while enhancing chip performance and power efficiency.

Backside Power Delivery in TSMC A16 Process: A new innovation that stood out was the backside power delivery system, which promises more efficient power routing and reduced energy consumption. This method helps manage the demands of trillion-transistor architectures by optimizing signal integrity and chip density.

Synopsys IP Solutions for 3DFabric Technologies: Updates were made to Synopsys’ UCIe and HBM4 IP solutions, which are crucial for TSMC’s 3DFabric technologies, including CoWoS (Chip on Wafer on Substrate) and SoIC (System on Integrated Chips). These updates further improve bandwidth and energy efficiency in multi-die designs.

3DIC Compiler, 3DSO.ai and Multi-Physics Flow: One of the more notable announcements involved the enhancement of Synopsys’ 3DIC Compiler platform and 3DSO.ai to address the complexities of multi-die designs and offer AI-driven multi-physics analysis during the design process, helping to streamline system-level integration.

TSMC Cloud Certification for Accelerated Design: To further accelerate the design process, Synopsys and TSMC have also enabled Synopsys EDA tools on the cloud, certified through TSMC’s Cloud Certification. This provides mutual customers with cloud-ready EDA tools that not only deliver accurate QoR but also seamlessly integrate with TSMC’s advanced process technologies.

The Importance of Multi-Die, 3DIC, and Multi-Physics Design

As semiconductor technology pushes beyond the traditional limits of Moore’s Law, multi-die designs and 3DICs have become essential for enhancing performance and density. These technologies allow for multiple dies, each with its own specialized function, to be stacked or placed side-by-side within a single package. However, the integration of these dies—especially when combining electronic ICs with photonic ICs—introduces significant design challenges.

One of the most pressing issues in multi-die design is thermal management. As multiple heat-generating dies are placed in close proximity, the risk of overheating increases, which can degrade performance and shorten the lifespan of the chip. Additionally, electromagnetic interference (EMI), signal integrity, and power distribution present further challenges that designers must account for during early-stage development.

This is where multi-physics analysis plays a critical role. Multi-physics analysis is the process of evaluating how different physical phenomena—such as heat dissipation, mechanical stress, and electrical signals—interact with one another within a chip package. Without an understanding of these interactions, it becomes nearly impossible to design reliable and efficient multi-die systems.

Synopsys Solutions for Multi-Die and 3DIC Challenges

Synopsys is at the forefront of addressing these challenges through its AI-powered solutions, many of which were updated or introduced during the TSMC OIP Ecosystem Forum. These tools are specifically designed to address the complexity of multi-die designs and 3DICs, where early-stage analysis and optimization are crucial for success.

AI-Driven EDA with Synopsys.ai

One of the most significant updates came from Synopsys.ai, which is now optimized for TSMC’s N2 process technology. This suite allows designers to leverage AI to improve design efficiency and reduce the time needed to move designs to production. By incorporating AI into the design process, Synopsys.ai helps engineers navigate the vast array of potential design configurations, ensuring that the most optimal solutions are chosen for performance, power efficiency, and thermal management.

“Synopsys’ certified Custom Compiler and PrimeSim solutions provide the performance and productivity gains that enable our designers to meet the silicon demands of high-performance analog design on the TSMC N2 process,” said Ching San Wu, Corporate VP at MediaTek in Synopsys’ news release. “Expanding our collaboration with Synopsys makes it possible for us to leverage the full potential of their AI-driven flow to accelerate our design migration and optimization efforts, improving the process required for delivering our industry-leading SoCs to multiple verticals.”

3DIC Compiler and 3DSO.ai for Multi-Die Systems

These tools enable designers to conduct multi-physics analysis early in the design process, which is essential for optimizing thermal and power management, signal integrity, and mechanical stability in multi-die systems. By identifying potential issues—such as hotspots or signal degradation—early in the process, designers can make informed adjustments before reaching the later stages of development, thus avoiding costly redesigns.

3DSO.ai leverages AI to analyze complex multi-die configurations, allowing engineers to test a wide range of potential scenarios in a fraction of the time it would take using traditional methods. This capability is critical as designs become more complex, with tens of thousands of possible combinations for how dies are stacked, interconnected, and cooled.

TSMC-certified Synopsys 3DIC Compiler’s compatibility with TSMC’s SoIC and CoWoS technologies further solidify its position as a leading platform for multi-die designs. This ensures seamless collaboration across design architecture and planning, design implementation, and signoff teams, enabling efficient 3DIC development for cutting-edge applications.

These technologies are critical for enabling the heterogeneous integration of dies in 3DIC systems, which helps overcome traditional scaling challenges such as thermal management and signal integrity.

As a demonstration vehicle, Synopsys achieved a successful tapeout recently, of a test chip featuring a multi-die design using TSMC’s CoWoS advanced packaging technology. This test chip leveraged TSMC’s 3DFabric technology and Synopsys’ multi-die solutions, including silicon-proven UCIe IP, 3DIC Compiler unified exploration-to-signoff platform, and the 3DSO.ai AI-driven optimization solution. The Figure below showcases the level of system analysis and optimization enabled by Synopsys 3DSO.ai. The test chip demonstrated unmatched performance reliability.

Figure: Synopsys 3DSO.ai AI-enabled system analysis and optimization 

Optimizing Power Delivery with Backside Power Innovations

The new backside power delivery capability, introduced through TSMC’s A16 process, represents a critical leap forward in ensuring power integrity in multi-die systems. By routing power through the backside of the chip, more space is made available on the front for signal routing and transistor placement. This helps reduce energy consumption while also enhancing signal integrity, ensuring that trillion-transistor designs can operate efficiently and reliably.

Summary

The announcements made by Synopsys at the TSMC OIP Ecosystem Forum underscore the growing importance of multi-die architectures, 3DIC systems, and multi-physics analysis in semiconductor design. With new AI-driven tools and key updates to existing solutions, Synopsys is helping engineers overcome the complex challenges posed by trillion-transistor designs and multi-die integration.

By leveraging Synopsys’ advanced EDA tools, platforms and IP, engineers can now address critical issues—like thermal management, signal integrity, and power distribution—at the earliest stages of the design process. This proactive approach not only improves design efficiency but also ensures that the final product meets the stringent performance requirements of AI, HPC, and other next-generation applications.

You can read the Synopsys announcement in its entirety here, and more details on the test chip tapeout here.

Also Read:

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)

Synopsys Powers World’s Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps

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TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC 16th OIP Ecosystem Forum First Thoughts
by Daniel Nenni on 09-26-2024 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

TSMC Advanced Technology Roadmap 2024

Even though this is the 16th OIP event please remember that TSMC has been working closely with EDA and IP companies for 20+ years with reference flows and other design enablement and silicon verification activities. The father of OIP officially is Dr. Morris Chang who named it the Grand Alliance. However, Dr. Cliff Hou is the one who actually created the OIP which is now the largest and strongest ecosystem in the history of semiconductors.

I spent a good portion of my career working with EDA and IP companies on foundry partnerships as well as foundries as a customer strategist. In fact, I still do and it is one of the most rewarding experiences of my career. Hsinchu was my second home for many years and the hospitality of the Taiwan people is unmatched. That same hospitality is a big part of the TSMC culture and part of the reason why they are the most trusted technology and capacity provider.

Bottom line: If anyone thinks this 20+ years of customer centric collaboration can be replicated or reproduced, it cannot, the OIP is a moving target, it expands and gets stronger every year. An ecosystem is also driven by the success of the company and in no part of history has TSMC been MORE successful than today, my opinion.

We will be covering the event in more detail next week but I wanted to share my first thoughts starting with a quote from a blog published yesterday by Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC. I met Dan 20 years ago when he was at Chartered Semiconductor. For the last 17 years he has been at TSMC where he started as Deputy Director of the TSMC IP Alliance (working for Cliff Hou) which is now a big part of the TSMC OIP.

Advancing 3D IC Design for AI Innovation by Dan Kochpatcharin

“Our collaboration with TSMC on advanced silicon solutions for our AWS-designed Nitro, Graviton, Trainium, and Inferentia chips enables us to push the boundaries of advanced process and packaging technologies, providing our customers with the best price performance for virtually any workload running on AWS.” – Gary Szilagyi, vice president, Annapurna Labs at AWS

Readers of the SemiWiki Forum will get this inside joke and if you think this quote from AWS is a coincidence you are wrong. C.C. Wei has a very competitive sense of humor!

Dr. L.C. Lu (Vice President of Research & Development / Design & Technology Platform) did the keynote which was quite good. I first met L.C. when he was in charge of the internal TSMC IP group working for Cliff Hou. He is a very smart no nonsense guy who is also a great leader. Coincidentally, L.C. and CC Wei both have P.h.D.s from Yale.

Some of the slides were very similar to the earlier TSMC Symposium slides which tells you that TSMC means what it says and says what it means. There were no schedule changes, it was all about implementation, implementation, and implementation.

L.C. did an interesting update on Design-Technology Co-Optimization (DTCO). I first heard of DTCO in 2022 and it really is the combination of design and process optimization. I do know customers who are using it but this is the first time I have seen actual silicon results. Remember, this is two years in the making for N3 FinFlex.

The numbers L.C. shared were impressive. In order to do real DTCO a foundry has to have both strong customer and EDA support and TSMC has the strongest. For energy efficiency (power savings) N3 customers are seeing 8%-20% power reductions and 6%-38% improvement in logic density depending on the fin configuration.

L.C. also shared DTCO numbers for N2 NanoFlex and the coming A16 SPR (Super Power Rail) which were all in the double digits (11%-30%). I do know quite a few customers who are designing to N2, in fact, it is just about all of TSMC’s N3 customers I am told. It will be interesting to see more customer numbers next year.

L.C. talked about packaging as well which we will cover in another blog but let me tell you this: By the end of 2024 CoWos will have more than 150 tape-outs from more than 25 different companies! And last I heard TSMC CoWos capacity will more than quadruple from 2023 levels by the end of 2026. Packaging is one of the reasons why I feel that the semiconductor industry has never been more exciting than it is today, absolutely!

Also Read:

TSMC OIP Ecosystem Forum Preview 2024

TSMC 16th OIP Ecosystem Forum First Thoughts

TSMC’s Business Update and Launch of a New Strategy

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TSMC OIP Ecosystem Forum Preview 2024

TSMC OIP Ecosystem Forum Preview 2024
by Daniel Nenni on 09-19-2024 at 10:00 am
Categories: Events, Foundries, TSMC

TSMC OIP 2024

The 2024 live conferences have been well attended thus far and there are many more to come. The next big event in Silicon Valley is the TSMC Global OIP Ecosystem Forum on September 25th at the Santa Clara Convention Center. I expect a big crowd filled with both customers and partners.

This is the 16th year of OIP and it has been an honor to be a part of it. The importance of semiconductor ecosystems is greatly understated as is the importance of the TSMC OIP Ecosystem.

The big change I have seen over the last few years is momentum. The FinFET era has gained an incredible amount of ecosystem strength and the foundation of course is TSMC. When we hit 5nm the tide changed in TSMC’s favor with a huge amount of TSMC N5 EDA, IP, and ASIC services support. In fact, there were a record setting number of tape-outs on this node. This momentum has increased at 3nm with TSMC N3 (the final FinFET node) having the strongest ecosystem support and tape-outs in the history of the fabless ecosystem in my experience.

The momentum is continuing with N2 which will be the first GAA node for TSMC. Rumor has it N2 will have comparable tape-outs with N3. It is too soon to say what will happen with the angstrom era but my guess is that semiconductor innovation and Moore’s Law will continue in one form or another.

A final thought on the ecosystem, while it appears that IDM foundries have more R&D strength than pure-play foundries I can assure you that is not the case. The TSMC OIP Ecosystem, for example, includes the largest catalog of silicon verified IP in the history of the semiconductor industry. IP companies first develop IP in partnership with TSMC to leverage the massive TSMC customer base. In comparison, the IDM foundries pay millions of dollars to port select IP to each of their processes to encourage customer demand.

Throughout the FinFET era foundries, customers and partners have spent hundreds of billions of R&D dollars in support of the fabless semiconductor ecosystem which will get the semiconductor industry to the one trillion dollar mark by the end of this decade, absolutely.

Here is the event promo:

Get ready for a transformative event that will spark innovations of today and tomorrow’s semiconductor designs at the 2024 TSMC Global Open Innovation Platform (OIP) Ecosystem Forum!

This year’s forum is set to ignite excitement with a focus on how AI is transforming chip design and the latest advances in 3DIC system design. Join industry trailblazers and TSMC’s ecosystem partners for an inside look at the latest innovations and breakthroughs.

Through a series of compelling, multi-track presentations, you’ll witness firsthand how the ecosystem is collaborating to address critical design challenges and leverage AI in chip design processes.

Engage with thought leaders and innovators at this unique event, available both in-person and online across major global locations, including North America, Japan, Taiwan, China, Europe, and Israel.

Don’t miss out on this opportunity to connect with the forefront of semiconductor technology.

Get the latest on:
• Emerging challenges in advanced node design and corresponding design flows and methodologies for N3, N2, and A16 processes..

• The latest updates on TSMC’s 3DFabric chip stacking and advanced packaging technologies including InFO, CoWoS®, and TSMC-SoIC®, 3DFabric Alliance, and 3Dblox standard, along with innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications.

• Comprehensive design solutions for specialty technologies, enabling ultra-low power, ultra-low voltage, analog migration, RF, mmWave, and automotive designs, targeting 5G, automotive, and IoT applications.

• Ecosystem-specific AI-assisted design flow implementations for enhanced productivity and optimization in 2D and 3D IC design.

• Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.

REGISTER NOW

Also Read:

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Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV

Application-Specific Lithography: Patterning 5nm 5.5-Track Metal by DUV
by Fred Chen on 08-08-2024 at 6:00 am
Categories: Lithography, TSMC
1 Comment

Application Specific Lithography I

At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track cell, this indicates a metal track pitch of 35 nm, while for the 5.5-track cell, the pitch is 38 nm (Figure 1). Just a 3 nm difference in pitch matters a lot for the patterning approach. As will be shown below, choosing the 5.5-track cell for DUV patterning makes a lot of sense.

Figure 1. 210 nm cell height means 38 nm track pitch for 5.5 tracks (left) or 35 nm track pitch for 6 tracks (left).

Extending the 7nm DUV Approach to 5nm

The 5.5-track metal pitch of 38 nm is at the limit of DUV double patterning. It can therefore reuse the same approach used in 7nm, where the 6-track cell metal pitch was 40 nm [3]. This can be as simple as self-aligned double patterning followed by two self-aligned cut blocks, one for each material to be etched (core or gap) (Figure 2). The minimum pitch of the cut blocks (for each material) is 76 nm, allowing a single exposure.

Figure 2. SADP followed by two self-aligned cut blocks (one for the core material, one for the gap material). Process sequence from left to right: (i) SADP (core lithography followed by spacer deposition and etchback, and gapfill; (ii) cut block lithography for exposing gap material to be etched; (iii) refill of cut block for gap material; (iv) cut block lithography for exposing core material to be etched; (v) refill of cut block for core material. Self-aligned vias (not shown) may be partially etched after the block formation [4].

In lieu of SADP, SALELE [5] may be used instead. This would add an extra mask for the gap material, resulting in a total of four mask exposures needed.

Going Below 38 nm Pitch: Hitting the Multipatterning Barrier

For the 3nm node, it is expected that the metal track pitch will go below 30 nm [6]. Any pitch below 38 nm would entail the use of substantially more DUV multipatterning [7]. Yet a comparable amount of multipatterning could also be expected even for EUV, as the minimum pitch from photoelectron spread can be effectively 40-50 nm for a typical EUV resist [8,9]. The edge definition for a 25 nm half-pitch 60 mJ/cm2 exposure is heavily affected by both the photon shot noise and the photoelectron spread (Figure 3).

Figure 3. 25 nm half-pitch electron distribution image exposed with an incident EUV dose of 60 mJ/cm2 (13 mJ/cm2 absorbed), with a 7.5 nm Gaussian blur to represent the electron spread function given in ref. [9]. A 1 nm pixel is used, with 4 secondary electrons per photoelectron.

5nm For All?

The 5.5-track cell provides an easy migration path from 7nm to 5nm using DUV double patterning. Potentially, this is one of the easier ways for Chinese companies to catch up at 5nm, although clearly that would be as far as they can take it.

References

[1] G. Yeap et al., IEDM 2019, Figure 5.

[2] https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

[3] https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7nm-and-the-snapdragon-855-dtco/#google_vignette

[4] F. Chen, Self-Aligned Block Redistribution and Expansion for Improving Multipatterning Productivity, https://www.linkedin.com/pulse/self-aligned-block-redistribution-expansion-improving-frederick-chen-rgnwc/

[5] Y. Drissi et al., Proc. SPIE 10962, 109620V (2019).

[6] https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/

[7] F. Chen, Extension of DUV Multipatterning Toward 3nm, https://semiwiki.com/lithography/336182-extension-of-duv-multipatterning-toward-3nm/, https://www.linkedin.com/pulse/extension-duv-multipatterning-toward-3nm-frederick-chen/

[8] F. Chen, Why NA is Not Relevant to Resolution in EUV Lithography, https://www.linkedin.com/pulse/why-na-relevant-resolution-euv-lithography-frederick-chen-ytnoc, https://semiwiki.com/lithography/344672-why-na-is-not-relevant-to-resolution-in-euv-lithography/

[9] T. Kozawa et al., JVST B 25, 2481 (2007).

Also Read:

Why NA is Not Relevant to Resolution in EUV Lithography

Intel High NA Adoption

Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity

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TSMC’s Business Update and Launch of a New Strategy

TSMC’s Business Update and Launch of a New Strategy
by Claus Aasholm on 07-30-2024 at 10:00 am
Categories: AI, Foundries, Semiconductor Business Intelligence, Semiconductor Services, TSMC

TSMC Fab Utilization 2024

What looks like a modest market expansion strategy is all but modest.

Insights into the Semiconductor Industry and the Semiconductor Supply Chain.

As usual, when TSMC reports, the Semiconductor industry gets a spray of insights that help understand what goes on in other areas of the industry. This time, TSMC gave more insight into their new Foundry 2.0 strategy, which will be covered later in this post.

The Q2-2024 result was a new revenue record indicating that the Semiconductor industry is out of the downcycle and ready to aim for new highs.

However, TSMC’s gross and operating profits have not returned to the same levels as last time, when revenue was over $20B/qtr. This is a new situation that needs to be uncovered.

Semiconductor manufacturing companies need to spend significant capital every quarter to maintain and service their equipment. Spending at the maintenance capex level ensures that manufacturing capacity does not decline.

From the end of 2020 until the end of 2023, TSMC made a significant capex investment above maintenance. The company then dropped capex to just above maintenance. This capacity is now flowing online, which has lowered TSMC’s utilisation revenue. The TSMC of Q2-24 has a lot more capacity at the last peak.

TSMC’s management did report increasing manufacturing utilisation, which means there is still spare capacity, although it might not be the capacity that TSMC needs.

There were other levers of Gross margin revealed in the investor call.

While the increasing manufacturing activity combined with the payment of Subsidies and selective price increases lifted the gross margin, there were also headwinds.

Inflation is increasing the cost of materials. As Taiwan’s largest electricity consumer, TSMC depends on grid expansion to fuel future growth. The investment in new and cleaner electricity is increasing electricity prices.

Also, the higher operating costs of the future manufacturing facilities in Arizona and Kumamoto would negatively impact gross margins.

Lastly, the company mentioned the conversion from 5 nm to 2 nm. It was earlier indicated that this was only Apple, but now it looks like TSMC is under great pressure from more of its HPC customers to migrate to 2nm.

Migrating customers takes time and effort, and it also takes time before manufacturing is sufficiently stable to generate good yields and become economically viable.

The market view

Unsurprisingly, TSMC is increasingly becoming THE supplier to the high-performance computing industry, as seen in the Q2-24 share of divisional revenue. Mobile is still significant, mainly due to Apple, but it is decreasing in share.

A revenue timeline shows the growth in Q2-24 comes from a step function increase in HPC revenue.

The annual growth rate for High-Performance Computing has been impressive, but the quarterly growth rate is even higher. This represents 145% CAGR in HPC.

HPC’s revenue share is increasing relentlessly, and TSMC is becoming a high-performance computing company. This is one of the drivers towards TSMC’s new Foundry 2.0 strategy.

Technology

While Apple has made a long-term commitment to TSMC to obtain exclusivity to the new 2N process, this is not likely to last as long as Apple’s exclusivity to the 3nm process, which has lasted for a year.

TSMC expect the business transition to 2nm will be faster and involve more products than the transition to 3 and 5nm combined over the first two years.

This means more TSMC clients than just Apple (from 3nm) want to get to 2nm. Not surprisingly this will be Nvidia (from 4/5nm), AMD & Intel (from 5nm) as the main clients

It took the 3-5nm business four years to reach 50% of the total revenue, while it only took 3nm 2 quarters to get 15%.

A comparison between HPC and 3nm revenue shows a similar trajectory.

As Apple has been the only 3nm customer up until now, it would be natural to assume that the growth spike is due to Apple, but this is likely not the case.

Apple being a consumer oriented company has a very specific buying pattern due to the seasonality of its business.

While the Apple Cogs also represent mobile business and other, this pattern can be seen in the TSMC 3nm business also. Q3 and Q4 up and Q1 down.

You would expect the Apple 3nm business to go down in Q2 also. It likely did but TSMC’s 3nm business grew by 84% in Q2-24 so something else is going on.

The jump in revenue is likely to come from one of the 5nm customers of and as the 5nm revenue did not decline, it is a new product.

While it could be Nvidia, the AI giant is likely busy selling Blackwell products that is based on TSMC’s 5nm (4) process.

More likely this is Intel’s Lunar Lake or AMD’s Instinct series or an upgrade of the Zen 5. Both Intel and AMD is reporting soon and this article will be updated. From a strategic perspective, TSMC is moving from few customers using the leading edge technology to many. This also means TSMC is getting more important for its customers in High Performance Computing.

Technology Development

There is a good reason TSMC’s clients want to get to 2nm and even better technologies (N16). The performance gains are significant.

The relative performance improvements (in layman’s terms) can be seen below. Power Improvements (at similar speed) or Speed improvement (at similar power):

N16 is best used for specific HPC products with complex signal routes and dense power delivery and work. Volume production is scheduled for the second half of 2026

TSMC normally introduces intermediary upgrades for each of their processes and the benefits can be significant as seen in the N2P process. It is almost like an entire new process node but with less risk and cost. It will be incredibly attractive for the AI GPU combattants to get to these nodes as fast as possible. The balance of power is leaning more towards TSMC.

Cowos Capacity

From a strategic perspective, advanced packaging is becoming incredibly important and the main driver behind the Foundry 2.0 Strategy

Even though TSMC is adding as much advanced packaging technology as possible, it is nowhere near fulfilling the demand. TSMC expect to grow capacity by 60% CAGR but will not be able to meet demand before sometime during 2026 at best.

Margins have been low but are improving to a level close to corporate average margin as yields improve. CoWoS is the main reason that TSMC is changing its strategy to 2.0. All of the HPC customers will need advanced packaging to integrate High Bandwidth memory on an interposer. Later on this will be a need for PC processors and everything else AI.

The new 2.0 Foundry Strategy:

While the Foundry 2.0 strategy looks like a market expansion strategy from the $125B (2023) Foundry markets to add the packaging market of $135B bringing the total addressable market for TSMC to $250B. This changes TSMC’s market share from 55.3% to 28% in the new definition.

Apart from market expansion, Foundry 2.0 also aligns closely with the changed need of the top HPC customers, Apple, Nvidia, Intel, AMD and Broadcom. TMSC can basically deliver everything but the memory element of the CPU and GPU boards.

From a technology perspective, the move makes TSMC less dependent of the continuation of Moore’s law predicting continously smaller 2D geometries as the advanced packaging effectively opens up for 3D integration and technology advancement.

It represents the transformation of TSMC from a components company to a subsystems company, just like Nvidia’s transformation from GPU to AI Server boards.

As Nvidia developed Blackwell, it became obvious that the silicon for the GPU itself got diluted. The introduction of more memory, Silicon interposers and large slabs of advanced substrates, made the GPU share of the BOM decline. The Foundry 2.0 strategy is also aimed at controlling more of the supply chain in order to maintain TSMC’s importance as supplier to the CPU and GPU customers.

The capital allocation strategy, reveals the current fiscal importance of each of the main areas of TSMC business. If we didn’t know it, TSMC is still an advanced logic node company and that will continue. The new advance packaging, test and mass making (assembly??) will be allocated 10% of the total CapEx budget which is 31B$ in 2024.

While this sounds modest, the capital requirements for the Test and Packaging (OSAT) companies is a lot less than for semiconductor manufacturing. The largest OSAT companies are ASE and Amkor and they have CapEx spend of and estimated 2.5B$ in 2024. TSMC is dead serious about entering this industry and the established companies need to be on their toes.

Conclusion

TSMC’s new strategy has a title that completely lacks imagination but the strategy itself is very well developed and also very ambitious. While Intel and Samsung are busy figuring out how to get their advanced foundry nodes to work and finding customer for them, TSMC is expanding its silicon leadership into advanced packaging becoming a more important supplier to the key AI customers. This will also increase TSMC’s bargaining situation making the company able to command more of the value generation in AI if TSMC is not as modest and humble as normal.

Also Read:

TSMC Foundry 2.0 and Intel IDM 2.0

Q&A With TSMC on Next-Gen Foundry

Will Semiconductor earnings live up to the Investor hype?

 

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TSMC Foundry 2.0 and Intel IDM 2.0

TSMC Foundry 2.0 and Intel IDM 2.0
by Daniel Nenni on 07-22-2024 at 10:00 am
Categories: 3D IC, Foundries, TSMC
7 Comments

TSMC 2Q2024 Investor Call

When Intel entered the foundry business with IDM 2.0 I was impressed. Yes, Intel had tried the foundry business before but this time they changed the face of the company with IDM 2.0 and went “all-in” so to speak. The progress has been impressive and today I think Intel is well positioned to capture the NOT TSMC business by providing a trusted alternative to the TSMC leading edge business. The one trillion dollar questions is: Will Intel take business away from TSMC on a competitive basis? I certainly hope so, for the greater good of the semiconductor industry.

On the most recent TSMC investor call, which is the first call with C.C. Wei as Chairman and CEO, TSMC branded their foundry strategy as Foundry 2.0. It is not a change of strategy, it is a new branding based on what TMSC has been successfully doing for years now, adding additional products and services to keep customers engaged. 3D IC packaging is a clear example but certainly not the only one. The Foundry 2.0 brand is well earned and is clearly targeted at Intel IDM 2.0 which I think is funny and a great example of CC Wei’s sharp wit.

I thought for sure that Intel 18A would be the breakout foundry node for Intel but according to the TSMC investor call, that is not the case. TSMC N3 was a runaway hit with 100% of the major design wins. Even Intel used TSMC N3. I hadn’t seen anything like this since TSMC 28nm which was on allocation as a result of being the only viable 28nm HKMG node out of the gate. History repeated itself with N3 due to the delay of 3nm alternatives. This made the TSMC ecosystem the strongest I have ever witnessed with both the domination of N3 and TSMC’s rapidly expanding packaging success. I had originally thought that some customers would stick with N3 until the second generation of N2 appeared but I was wrong. On yesterday’s investor call:

CC Wei: We expect the number of the new tape-outs for 2-nanometer technologies in its first two years to be higher than both 3-nanometer and 5-nanometer in their first two years. N2 will deliver full load performance and power benefit, with 10 to 15 speed improvement at the same power, or 25% to 30% power improvement at the same speed, and more than 15% chip density increase as compared with the N3E.

CC had mentioned this before but I can now confirm this based on my hallway discussions inside the ecosystem at recent conferences: N2 designs are in progress and will start taping out towards the end of this year.

I really don’t think the TSMC ecosystem gets enough credit, especially after the overwhelming success of N3, but the N2 node is a force in itself:

CC Wei: N2 technology development is progressing well, with device performance and yield on track or ahead of plan. N2 is on track for volume production in 2025 with a ramp profile similar to N3. With our strategy of continuous enhancement, we also introduce N2P as an extension of our N2 family. N2P features a further 5% performance at the same power or 5% to 10% power benefit at the same speed on top of N2. N2P will support both smartphone and HPC applications, and volume production is scheduled for the second half of 2026. We also introduce A16 as our next nanosheet-based technology, featuring Super Power Rail, or SPR, as a separate offering.

And, of course, the TSMC freight train continues:

CC Wei: TSMC’s SPR is an innovative, best-in-class backside power delivery solution that is forcing the industry to incorporate another backside contact scheme to preserve gate density and device with flexibility. Compared with N2P, A16 provides a further 8% to 10% speed improvement at the same power, or 15% to 20% power improvement at the same speed, and additional 7% to 10% chip density gain. A16 is best suited for specific HPC products with complex signal routes and dense power delivery network. Volume production is scheduled for the second half of 2026. We believe N2, N2P, A16, and its derivative will further extend our technology leadership position and enable TSMC to capture the growth opportunities way into the future.

Congratulations to TSMC on their continued success, it is well deserved. I also congratulate the Intel Foundry team for making a difference and I hope the 14A foundry node will give the industry a trusted alternative to TSMC out of the starting gate.  In my opinion, had it not been for Intel and of course CC Wei’s leadership and response to Intel’s challenge, we as an industry would not be quickly approaching the one trillion dollar revenue mark. Say what you want about Nvidia, but as Jensen Huang openly admits, TSMC and the foundry business is the real hero of the semiconductor industry, absolutely.

Also Read:

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What if China doesn’t want TSMC’s factories but wants to take them out?

What if China doesn’t want TSMC’s factories but wants to take them out?
by Claus Aasholm on 07-02-2024 at 10:00 am
Categories: China, Foundries, Samsung Foundry, Semiconductor Business Intelligence, Semiconductor Services, TSMC
11 Comments

Foundry Numbers 2024

Insights into the Semiconductor Industry and the Semiconductor Supply Chain

I am not an expert in geopolitical issues, but lately, my research has begun to worry me. As I was preparing to be interviewed for Chinese media, I was in my “Chinese Zone”, adapting to what is palatable to a Chinese audience. Maybe my mode provoked the thought:

Who would benefit from eradicating the entire Taiwanese Semiconductor industry?

What if China is not deterred by potentially mined TSMC factories and ASML kill switches? What if the reunification plan is based on eradicating the TSMC factories and the Semiconductor supply chain in Taiwan and beyond?

For the first time, I can see the outline of a military invasion plan that can significantly benefit China, but the implications are scary. While I have no indications that this is actually about to happen, this is within the “Strong Man” thinking. This article describes that scenario and its implications.

The Three Reunifications Scenario

My upbringing in a small, peaceful country devoid of geopolitical ambitions during the Cold War has shaped my understanding of these issues. Living less than 200km from the Warsaw Pact border, I witnessed the system before and after the wall fell. The system didn’t crumble with the wall. It retreated to Russia, reorganising under the guise of democracy and economic reform. I experienced this firsthand during my extensive travels in Russia, not just the “civilised” parts.’

I’m not writing this in my mother tongue and only a few comprehend what it means to be Danish. As a small nation, we are not imperial and don’t need nationalism, we need cooperation with other countries, primarily in the coal union that brought peace to the parts of Europe that formed the EU.

Although not an expert, I feel qualified to give my view of the geopolitical situation, and I have no problem with others disagreeing with my assessment.

The background

After the fall of the Soviet Union, a new US-led, rules-based world order began. It was based on alliances and corporations and supported civil rights, free speech, and democracy. It was the birth of globalism.

The Semiconductor supply chain evolved and grew in locations where it made the most sense, and nobody interjected or tried to dictate this development. Most US semiconductor companies were happy to eliminate the hassle of making chips that could be made better and cheaper in Asia.

The world is moving from the rule of law to the law of rulers

That order is now breaking down. The US standings in the world have deteriorated due to long wars with little plans for the aftermath and the increasing division of the US society. Trust in elections and institutions is at an all-time low. The more the US tries to dictate the world order, the less it succeeds, as the USA has become unpredictable to the rest of the world. The outcome of a US election can now create two very different scenarios for the world order, and the election itself will be disrupted no matter what. A few votes in a swing state, a Florida judge or a Supreme Court decision can decide the election.

World order and Strong men

The breakdown of the rules-based world order got plenty of help from the outside. Democracy and free speech are not Strong Men’s favourite dishes. It goes against the dictator’s playbook, which has three chapters:

  • The Enemy Within – I alone can fix it
  • Prosperity – I am the system, and it is good for you
  • The external Enemy, I am the only one to protect you.

The enemy within is the tool to gain power. The breakdown of trust in politicians, institutions and society in general. It culminates when political opponents are hated more than external “enemies”.

For many years, Putin had a “deal” with the Russians that if they stayed out of politics, he would make them more prosperous, and he did. From the late nineties and 15 years on, the standard of living increased dramatically. But this was built on an organised cleptocracy that stole from the people and eventually ran out of steam.

Enter the external enemy. It is time to make Russia great again, first by covert little green men operations and later the full-scale invasion of Ukraine. As this did not go well, the enemy was changed from Ukraine to the West. “We are fighting the collective forces of the West.”

The overarching objective of a Strong Man is to keep power after securing it. Self-perseverance is key. If only a few per cent of the population starts to protest, you are in trouble. Stability is your friend.

Where Putin is deep in 3 and has transformed the entire Russian society into a war economy, President Xi is likely at the end of 2. The massive infrastructure and real estate investments are starting to look hollow, and economic growth is slowing. It’s time to make China great again.

Everyone is aware of China’s increasing military ambitions. Its claim to atolls in the South China Sea and naval conflicts with all its neighbours point to a new geopolitical reality.

The no-limits partnership between Russia and China and the latest treaty between North Korea and Russia opens up the possibility of a potentially devastating conflict to make Russia, Korea and China reunified and great again.

He who controls the present controls the past.
He who controls the past controls the future.
George Orwell, 1984

A vital element of the Strong Man’s storyline is the past. Everything was better, and we were stronger and a larger unified nation. If you have the ultimate power, you can make insurrections, nuclear accidents, and squares disappear. The past is no stranger to a strong man.

Ruler of the past (what is left)

While Western politicians come and go, China and Xi understand how to play the long game. The semiconductor industry has been a focus area for decades, while Western corporations cannot see beyond the quarterly boundary.

I slept relatively well at night, believing China couldn’t conquer Taiwan and preserve the Semiconductor industry. A scenario without winners that would set the world back 15 years or more.

I realised that a destructive reset could become a long-term advantage in a long game. If Xi were willing to turn back the clock 15 years, China could emerge as the winner of the past, of whatever was left.

Prelude

The Three Reunifications Scenario might not be the original plan, but it could have developed due to Russia’s invasion of Ukraine. This is the prelude that China has observed the overwhelming Russian war machine being degraded by drones and precision weapons from the West. It is unlikely that other invasions will differ, so any attempt to conserve part of the conquered industry is an illusion. Destruction is inevitable.

Diversion

Surprisingly, China has not commented much on the Russis-North Korea Defense pact. Why is China not uncomfortable with Little Rocket Man getting better rockets? Maybe because the next part of the plan is a North Korean attack on South Korea. This would further stretch Western military resources and deplete the already dwindling military resources. China could lean back and say: Not our problem. While it is unlikely that North Korea can conquer South Korea, it can destroy a lot of the South Korean Industry.

Finale

The West’s involvement in two wars of attrition forms the basis for an invasion of Taiwan. There is a limit to how many conflicts the US military and its Western allies can be in simultaneously. That might allow China to invade Taiwan without too much or any direct involvement from outside forces. With part of the US political establishment becoming more isolationistic, the West would likely be unable to handle three military flashpoints at a time.

Although I knew the tensions between Ukrainians and Russians first-hand, I was convinced Russia would not invade – I could not see the logic (maybe strongmen don’t use logic). I hope I am also wrong about the Three Reunifications Scenario. Unfortunately, I can see the logic in it from a Chinese perspective.

The current Manufacturing View:

Although not all companies have all manufacturing in their legal jurisdiction, it is the exception rather than the rule.

The distribution of semiconductor Property, Plant, and Equipment (PPE) gives a good overview of the manufacturing capacity from a geographic perspective. Chinese privately (state) owned companies are adding an estimated 35B$. These companies specialise in Memory, Micro, CPU, and mobile semiconductors.

While PPE includes other assets, these are very small for a Semiconductor Manufacturing Company. The Fabs and equipment dominate PPE. It can also be argued that PPE is higher per dollar of revenue in the US than in China and that advanced manufacturing takes more PPE value. These are all fair arguments to consider. Still, PPE is a much more solid number than most in the industry.

We divide manufacturing capacity into three categories:

  1. Integrated Device Manufacturing (IDM)
  2. Semiconductor Foundry
  3. Mixed Manufacturing

Traditionally, all semiconductor companies were IDMs that manufactured and sold branded products. With the emergence of TSMC, companies could choose to outsource manufacturing and go fabless. Some companies have chosen the mixed model and retained some manufacturing capacity while outsourcing the rest.

Property, Plant and Equipment $M, by Country of Incorporation, March 31st, 2024

The USA is still dominant despite some US capacity in other jurisdictions, so the physical location is elsewhere. Intel has Fabs in Ireland, Israel, and Malaysia, but most of its capacity is in the US. From a PPE perspective, Intel is not getting as much value from its manufacturing assets as TSMC is. This is a function of Intel making subpar manufacturing decisions, excluding Deep UV equipment. Despite these discrepancies, we still believe that a PPE analysis is solid and a source of good insights.

The PPE analysis shows that most of the chip manufacturing capacity is concentrated around the East China Sea, and 50% is in potential “Reunification” zones.

China’s 12% share of global PPE might sound low, but it is growing incredibly. Despite the US lead embargo, China still buys nearly half of the Western semiconductor tools sold, amounting to a roughly 31B$ annual run rate plus an additional 4B$ of Chinese tools. The embargo and Chips Act only accelerated this development.

The total Chinese PPE is projected to pass 100B$ within a year with these numbers. A near 50% growth will give China an estimated 18% global capacity.

If the semiconductor manufacturing capacity of South Korea and Taiwan is excluded, China will have a third of the global capacity by the end of the year. For every year that passes, China will gain more capacity than even the US.

With the exclusion, the total capacity, based on PPE, will decline from 550B$ to 300B$

Revenue versus Capacity

As global semiconductor revenue has been an average of $550B over the last couple of years, and the combined PPE is also around 550B$, it can be assumed that 1$ of PPE can generate 1$ of annual revenue. This might be too crude for accounts, but it can be used for this scenario.

Excluding Taiwanese and South Korean manufacturing, the world would be set back 15 years from a manufacturing standpoint. China would command 1/3rd of the capacity at the end of this year. This share would grow significantly every year any military action is delayed. Time is on China’s side.

How this will be devastating to the US

Based on the PPE analysis, the US would be a significant winner in the Three Reunifications Scenario, but there are some complications. The first is that the US capacity is concentrated in one company, Intel, which is not in the best of shapes. As with the other US semiconductor companies, Intel’s business heavily depends on the supply chain in Asia, especially the high-tech supply chain of Taiwan, Korea and Japan.

The destruction of the Semiconductor Supply Chain

The destruction will not only impact semiconductor manufacturing but also the semiconductor supply chain. A Korean conflict could impact US manufacturing positively, while the supply chain implications are minimal. A Taiwanese conflict, however, would be negative for the US. For the large US fabless companies it would be catastrophic and US rely a lot on the high tech Taiwanese supply chain.

The smaller and more sheltered Japanese and European Semiconductor industries are more sheltered and self-sufficient from a supply chain perspective and would likely fare better than the US.

Excluding Taiwanese and South Korean manufacturing, the world would be set back 15 years from a manufacturing standpoint. China would command 1/3rd of the capacity at the end of this year. This share would grow significantly every year any military action is delayed. Time is on China’s side.

How this will be devastating to the US

Based on the PPE analysis, the US would be a significant winner in the Three Reunifications Scenario, but there are some complications. The first is that the US capacity is concentrated in one company, Intel, which is not in the best of shapes. As with the other US semiconductor companies, Intel’s business heavily depends on the supply chain in Asia, especially the high-tech supply chain of Taiwan, Korea and Japan.

The destruction of the Semiconductor Supply Chain

The destruction will not only impact semiconductor manufacturing but also the semiconductor supply chain. A Korean conflict could impact US manufacturing positively, while the supply chain implications are minimal. A Taiwanese conflict, however, would be negative for the US. For the large US fabless companies it would be catastrophic and US rely a lot on the high tech Taiwanese supply chain.

The smaller and more sheltered Japanese and European Semiconductor industries are more sheltered and self-sufficient from a supply chain perspective and would likely fare better than the US.

China, however, would emerge as the winner. The Chinese semiconductor industry follows the deep tradition of locally building the entire supply chain. From raw goods to finished products.

As semiconductor materials manufacturing is not as PPE intensive as semiconductor manufacturing, it is more relevant to look at revenue:

According to SEMI research, in 2023, more than 35% of all Semiconductor materials outside Taiwan and South Korea will be in China.

Taking out most of the leading-edge manufacturing and supply chain would leave the Chinese semiconductor industry in the sweet spot, ready to serve the world. As the Chinese are experts in value chains, they are not likely to sell their semiconductors directly to the West, but they will be more than happy to sell them wrapped in products. Your next electronic products—phones, PCs, and Cars—might be Chinese, but you must wait until AI is back on the agenda, as the Semiconductor clock has reversed a few years.

It would serve many of Xi’s goals, including reunification, however ugly. An external enemy could be potentially humiliated by non-intervention. China is emerging as the number one country in semiconductors (based on mature nodes turned leading edge), with most of the high-tech manufacturing in the world.

As I started by saying: Fortunately, this is just a scenario….

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VLSI Technology Symposium – Intel describes i3 process, how does it measure up?

VLSI Technology Symposium – Intel describes i3 process, how does it measure up?
by Scotten Jones on 06-28-2024 at 6:00 am
Categories: Intel Foundry, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
20 Comments

Figure 1. Process Key Dimensions Comparison.

At the VLSI Technology Symposium this week Intel released details on their i3 process. Over the last four nodes Intel has had an interesting process progression. In 2019, 10nm finally entered production with both high performance and high-density standard cells. 10nm went through several iterations eventually resulting in i7, a high-performance cell only process. When we characterize process density, we always talk about the highest density logic standard cell, 10nm achieved just over 100 million transistors per millimeter squared density (MTx/mm2), i7 in in 2022 only achieved approximately 64 MTx/mm2 density because it only had high performance cells. i4 entered production in 2023 and is once again a high-performance cell only process and achieves approximately 130 MTx/mm2. Finally, i3 will enter production in 2024 on multiple Intel products providing both high performance and high-density cells. The high-density cells achieve approximately 148 MTx/mm2 transistor density.

The key dimensions for the processes are compared in figure 1.

Figure 1. Process Key Dimensions Comparison.

In figure 1 the values for 10nm and i7 are actual values measured by TechInsights on production parts, the i4 and i3 values are from the VLSI Technology papers on i4 [1], and i3 [2]. The cell height for i3 of 210nm is for high density cells, there is also a 240nm height high performance cell with the same density as the i4 process. 240nm height high performance cells are 3 fin devices the same at i4 and the 210nm high density cells are 2 fin devices with wide metal zero.

Figure 2 presents the density changes between the processes in graphics form.

From 32nm through 10nm Intel accelerated from  2.0x to 2.4x and then to 2.7x density improvements, but as is the case with other companies pushing the leading edge, i3 is a less than 2x density jump.

Figure 2. Intel Process Density Comparison.

Figure 3 is from the Intel presentation and presents more details on the i4 to i3 process shrink.

Figure 3. i4 to i3 Process Shrink.

The i3 process will offer multiple variants targeted at different applications.

  • i3 base process and i3-T with TSVs targeted at client, server and base die for chiplet applications.
  • i3-E offer native 1.2 volt I/O devices, deep N-wells, and long channel analog devices, and is targeted at chipsets and storage applications.
  • i3-PT targets high performance computing and AI with 9μm pitch TSVs and hybrid bonding.

Figure 4 summarizes the process variants.

Figure 4. i3 Process Variants.

i3 features:

  • Smaller M2 pitch than i4.
  • Better fin profile.
  • Utilizes dipoles to set threshold voltages, i4 does not use dipoles. Dipoles improve gate oxide reliability.
  • Offer 14, 18, and 21 metal layer options (counts include metal 0).
  • 4 threshold voltages, V:VT, LVT, SVT, HVT.
  • Contact optimization to provide less overlap capacitance.
  • More effective EUV usage, i4 was Intel’s first EUV process, i3 EUV processes are less complex.
  • Lower line resistance and capacitance than i4.
  • 5x lower leakage at the same drive current as i4.
  • Increased frequency and drive current with no hot carrier increase.
  • Interconnect delay is now approximately half of overall delay and the base process has better RC delay, the PT process is even better.
  • At the same power i3 HD cells provide 18% better performance than i4 HP cells.

Figure 5 presents the interconnect pitches for the 14, 18, and 21 metal options.

Figure 5. Interconnect Pitches.

Figure 6 illustrates the improvement in interconnect RC delay.

Figure 6. Interconnect RC Delay.

And finally, figure 7 illustrates the 18% performance improvement over i4.

Figure 7. Interconnect Delay Improvement.

During an analysts briefing session questions and answers session Intel disclosed the channels are all silicon, no silicon germanium channels. Also, i4 designs have been ported to i3 and they are seeing PPA improvements on the same designs.

i3 is currently in high volume manufacturing with multiple Intel products.

i3 clearly represents a significant improvement over i4.

Comparisons to competitors

i3 is a significant improvement over i4 but how does it compare to competitors?

TechInsights has analyzed density, performance, and cost of i3 versus Samsung and TSMC processes. That analysis is available in the TechInsights platform here (free registration required):

Conclusion

Intel’s i3 process is a significant step forward from Intel’s i4 process with better density and performance. Intel’s i3 process is a more competitive foundry process than previous generations. Cost is more in-line with other foundry processes, density is slightly lower than Samsung 3nm and much lower than TSMC 3nm, but it has the best performance of the “3nm” processes.

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TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design

TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
by Mike Gianfagna on 06-10-2024 at 6:00 am
Categories: 3D IC, Events, Foundries, TSMC
2 Comments

TSMC Advanced Packaging Overcomes the Complexities of Multi Die Design

The TSMC Technology Symposium provides a worldwide stage for TSMC to showcase its advanced technology impact and the extensive ecosystem that is part of the company’s vast reach. These events occur around the world and the schedule is winding down. TSMC covers many topics at its Technology Symposium, including industry-leading HPC, smartphone, IoT, and automotive platform solutions, 5nm, 4nm, 3nm, 2nm processes, ultra-low power, RF, embedded memory, power management, sensor technologies, and AI enablement. Capacity expansion and green manufacturing achievements were also discussed, along with TSMC’s Open Innovation Platform® ecosystem. These represent significant achievements for sure. For this post, I’d like to focus on another set of significant achievements in advanced packaging. This work has substantial implications for the future of the semiconductor industry. Let’s examine how TSMC advanced packaging overcomes the complexities of multi-die design.

Why Advanced Packaging is Important

Advanced packaging is a relatively new addition to the pure-play foundry model. It wasn’t all that long ago that packaging was a not-so-glamorous finishing requirement for a chip design that was outsourced to third parties. The design work was done by package engineers who got the final design thrown over the wall to fit into one of the standard package configurations. Today, package engineers are the rock stars of the design team. These folks are involved at the very beginning of the design and apply exotic materials and analysis tools to the project. The project isn’t real until the package engineer signs off that the design can indeed be assembled.

With this part of the design process becoming so critically important (and difficult) it’s no surprise that TSMC and other foundries stepped up to the challenge and made it part of the overall set of services provided. The driver for all this change can be traced back to three words: exponential complexity increase. For many years, exponential complexity increase was delivered by Moore’s Law in the form of larger and larger monolithic chips. Today, it takes more effort and cost to get to the next process node and when you finally get there the improvement isn’t as dramatic as it once was. On top of that, the size of new designs is so huge that it can’t fit on a single chip.

These trends have catalyzed a new era of exponential complexity increase, one that relies on heterogeneous integration of multiple dies (or chiplets) in a single package, and that has created the incredible focus and importance of advanced packaging as critical enabling technology. TSMC summarizes these trends nicely in the diagram below.

TSMC’s Advanced Packaging Technologies

TSMC presented many parts of its strategy to support advanced packaging and open the new era of heterogenous integration. These are the technology building blocks for TSMC’s 3DFabric™ Technology Portfolio:

  • CoWoS®: Chip-on-Wafer-on-Substrate is a 2.5D wafer-level multi-chip packaging technology that incorporates multiple dies side-by-side on a silicon interposer to achieve better interconnect density and performance. Individual chips are bonded through micro-bumps on a silicon interposer forming a chip-on-wafer (CoW).
  • InFO: Integrated Fan-Out wafer level packaging is a wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance. The InFO platform offers various package schemes in 2D and 3D that are optimized for specific applications.
  • TSMC-SoIC®: Is a service platform that provides front-end, 3D inter-chip (3D IC) stacking technologies for re-integration of chiplets partitioned from a system on chip (SoC). The resulting integrated chip outperforms the original SoC in system performance. It also affords the flexibility to integrate additional system functionalities. The platform is fully compatible with CoWoS and InFO, offering a powerful “3Dx3D” system-level solution.

The figure below summarizes how the pieces fit together.

Getting all this to work across the ecosystem requires collaboration. To that end, TSMC has established the 3DFabric Alliance to enable work with 21 industry partners to cover memory, substrate, testing and OSAT collaborations to lower 3DIC design barriers, improve STCO and accelerate 3DIC adoption. The group also drives 3DIC development in tools, flows, IP, and interoperability for the entire 3Dfabric stack. The figure below summarizes the group of organizations that are involved in this work.

There is so much effort going on to support advanced packaging at TSMC. I will conclude with one more example of this work. 3Dblox™ is a standard new language that will help make designing 3D ICs much easier. TSMC created 3Dblox alongside its EDA partners such as Ansys, Cadence, Intel, Siemens, and Synopsys to unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The figure below shows the progress that has been achieved with this effort.

3Dblox Roadmap

To Learn More

I have touched on only some of the great work going on at TSMC to create advanced packaging solutions to pave the way for the next era of multi-die, heterogeneous design. You can get more information about this important effort at TSMC here. And that’s how TSMC advanced packaging overcomes the complexities of multi-die design.

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