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When Intel entered the foundry business with IDM 2.0 I was impressed. Yes, Intel had tried the foundry business before but this time they changed the face of the company with IDM 2.0 and went “all-in” so to speak. The progress has been impressive and today I think Intel is well positioned to capture the NOT TSMC business by providing a trusted alternative to the TSMC leading edge business. The one trillion dollar questions is: Will Intel take business away from TSMC on a competitive basis? I certainly hope so, for the greater good of the semiconductor industry.
On the most recent TSMC investor call, which is the first call with C.C. Wei as Chairman and CEO, TSMC branded their foundry strategy as Foundry 2.0. It is not a change of strategy, it is a new branding based on what TMSC has been successfully doing for years now, adding additional products and services to keep customers engaged. 3D IC packaging is a clear example but certainly not the only one. The Foundry 2.0 brand is well earned and is clearly targeted at Intel IDM 2.0 which I think is funny and a great example of CC Wei’s sharp wit.
I thought for sure that Intel 18A would be the breakout foundry node for Intel but according to the TSMC investor call, that is not the case. TSMC N3 was a runaway hit with 100% of the major design wins. Even Intel used TSMC N3. I hadn’t seen anything like this since TSMC 28nm which was on allocation as a result of being the only viable 28nm HKMG node out of the gate. History repeated itself with N3 due to the delay of 3nm alternatives. This made the TSMC ecosystem the strongest I have ever witnessed with both the domination of N3 and TSMC’s rapidly expanding packaging success. I had originally thought that some customers would stick with N3 until the second generation of N2 appeared but I was wrong. On yesterday’s investor call:
CC Wei: We expect the number of the new tape-outs for 2-nanometer technologies in its first two years to be higher than both 3-nanometer and 5-nanometer in their first two years. N2 will deliver full load performance and power benefit, with 10 to 15 speed improvement at the same power, or 25% to 30% power improvement at the same speed, and more than 15% chip density increase as compared with the N3E.
CC had mentioned this before but I can now confirm this based on my hallway discussions inside the ecosystem at recent conferences: N2 designs are in progress and will start taping out towards the end of this year.
I really don’t think the TSMC ecosystem gets enough credit, especially after the overwhelming success of N3, but the N2 node is a force in itself:
CC Wei: N2 technology development is progressing well, with device performance and yield on track or ahead of plan. N2 is on track for volume production in 2025 with a ramp profile similar to N3. With our strategy of continuous enhancement, we also introduce N2P as an extension of our N2 family. N2P features a further 5% performance at the same power or 5% to 10% power benefit at the same speed on top of N2. N2P will support both smartphone and HPC applications, and volume production is scheduled for the second half of 2026. We also introduce A16 as our next nanosheet-based technology, featuring Super Power Rail, or SPR, as a separate offering.
And, of course, the TSMC freight train continues:
CC Wei: TSMC’s SPR is an innovative, best-in-class backside power delivery solution that is forcing the industry to incorporate another backside contact scheme to preserve gate density and device with flexibility. Compared with N2P, A16 provides a further 8% to 10% speed improvement at the same power, or 15% to 20% power improvement at the same speed, and additional 7% to 10% chip density gain. A16 is best suited for specific HPC products with complex signal routes and dense power delivery network. Volume production is scheduled for the second half of 2026. We believe N2, N2P, A16, and its derivative will further extend our technology leadership position and enable TSMC to capture the growth opportunities way into the future.
Congratulations to TSMC on their continued success, it is well deserved. I also congratulate the Intel Foundry team for making a difference and I hope the 14A foundry node will give the industry a trusted alternative to TSMC out of the starting gate. In my opinion, had it not been for Intel and of course CC Wei’s leadership and response to Intel’s challenge, we as an industry would not be quickly approaching the one trillion dollar revenue mark. Say what you want about Nvidia, but as Jensen Huang openly admits, TSMC and the foundry business is the real hero of the semiconductor industry, absolutely.
Insights into the Semiconductor Industry and the Semiconductor Supply Chain
I am not an expert in geopolitical issues, but lately, my research has begun to worry me. As I was preparing to be interviewed for Chinese media, I was in my “Chinese Zone”, adapting to what is palatable to a Chinese audience. Maybe my mode provoked the thought:
Who would benefit from eradicating the entire Taiwanese Semiconductor industry?
What if China is not deterred by potentially mined TSMC factories and ASML kill switches? What if the reunification plan is based on eradicating the TSMC factories and the Semiconductor supply chain in Taiwan and beyond?
For the first time, I can see the outline of a military invasion plan that can significantly benefit China, but the implications are scary. While I have no indications that this is actually about to happen, this is within the “Strong Man” thinking. This article describes that scenario and its implications.
The Three Reunifications Scenario
My upbringing in a small, peaceful country devoid of geopolitical ambitions during the Cold War has shaped my understanding of these issues. Living less than 200km from the Warsaw Pact border, I witnessed the system before and after the wall fell. The system didn’t crumble with the wall. It retreated to Russia, reorganising under the guise of democracy and economic reform. I experienced this firsthand during my extensive travels in Russia, not just the “civilised” parts.’
I’m not writing this in my mother tongue and only a few comprehend what it means to be Danish. As a small nation, we are not imperial and don’t need nationalism, we need cooperation with other countries, primarily in the coal union that brought peace to the parts of Europe that formed the EU.
Although not an expert, I feel qualified to give my view of the geopolitical situation, and I have no problem with others disagreeing with my assessment.
The background
After the fall of the Soviet Union, a new US-led, rules-based world order began. It was based on alliances and corporations and supported civil rights, free speech, and democracy. It was the birth of globalism.
The Semiconductor supply chain evolved and grew in locations where it made the most sense, and nobody interjected or tried to dictate this development. Most US semiconductor companies were happy to eliminate the hassle of making chips that could be made better and cheaper in Asia.
The world is moving from the rule of law to the law of rulers
That order is now breaking down. The US standings in the world have deteriorated due to long wars with little plans for the aftermath and the increasing division of the US society. Trust in elections and institutions is at an all-time low. The more the US tries to dictate the world order, the less it succeeds, as the USA has become unpredictable to the rest of the world. The outcome of a US election can now create two very different scenarios for the world order, and the election itself will be disrupted no matter what. A few votes in a swing state, a Florida judge or a Supreme Court decision can decide the election.
World order and Strong men
The breakdown of the rules-based world order got plenty of help from the outside. Democracy and free speech are not Strong Men’s favourite dishes. It goes against the dictator’s playbook, which has three chapters:
The Enemy Within – I alone can fix it
Prosperity – I am the system, and it is good for you
The external Enemy, I am the only one to protect you.
The enemy within is the tool to gain power. The breakdown of trust in politicians, institutions and society in general. It culminates when political opponents are hated more than external “enemies”.
For many years, Putin had a “deal” with the Russians that if they stayed out of politics, he would make them more prosperous, and he did. From the late nineties and 15 years on, the standard of living increased dramatically. But this was built on an organised cleptocracy that stole from the people and eventually ran out of steam.
Enter the external enemy. It is time to make Russia great again, first by covert little green men operations and later the full-scale invasion of Ukraine. As this did not go well, the enemy was changed from Ukraine to the West. “We are fighting the collective forces of the West.”
The overarching objective of a Strong Man is to keep power after securing it. Self-perseverance is key. If only a few per cent of the population starts to protest, you are in trouble. Stability is your friend.
Where Putin is deep in 3 and has transformed the entire Russian society into a war economy, President Xi is likely at the end of 2. The massive infrastructure and real estate investments are starting to look hollow, and economic growth is slowing. It’s time to make China great again.
Everyone is aware of China’s increasing military ambitions. Its claim to atolls in the South China Sea and naval conflicts with all its neighbours point to a new geopolitical reality.
The no-limits partnership between Russia and China and the latest treaty between North Korea and Russia opens up the possibility of a potentially devastating conflict to make Russia, Korea and China reunified and great again.
He who controls the present controls the past. He who controls the past controls the future. George Orwell, 1984
A vital element of the Strong Man’s storyline is the past. Everything was better, and we were stronger and a larger unified nation. If you have the ultimate power, you can make insurrections, nuclear accidents, and squares disappear. The past is no stranger to a strong man.
Ruler of the past (what is left)
While Western politicians come and go, China and Xi understand how to play the long game. The semiconductor industry has been a focus area for decades, while Western corporations cannot see beyond the quarterly boundary.
I slept relatively well at night, believing China couldn’t conquer Taiwan and preserve the Semiconductor industry. A scenario without winners that would set the world back 15 years or more.
I realised that a destructive reset could become a long-term advantage in a long game. If Xi were willing to turn back the clock 15 years, China could emerge as the winner of the past, of whatever was left.
Prelude
The Three Reunifications Scenario might not be the original plan, but it could have developed due to Russia’s invasion of Ukraine. This is the prelude that China has observed the overwhelming Russian war machine being degraded by drones and precision weapons from the West. It is unlikely that other invasions will differ, so any attempt to conserve part of the conquered industry is an illusion. Destruction is inevitable.
Diversion
Surprisingly, China has not commented much on the Russis-North Korea Defense pact. Why is China not uncomfortable with Little Rocket Man getting better rockets? Maybe because the next part of the plan is a North Korean attack on South Korea. This would further stretch Western military resources and deplete the already dwindling military resources. China could lean back and say: Not our problem. While it is unlikely that North Korea can conquer South Korea, it can destroy a lot of the South Korean Industry.
Finale
The West’s involvement in two wars of attrition forms the basis for an invasion of Taiwan. There is a limit to how many conflicts the US military and its Western allies can be in simultaneously. That might allow China to invade Taiwan without too much or any direct involvement from outside forces. With part of the US political establishment becoming more isolationistic, the West would likely be unable to handle three military flashpoints at a time.
Although I knew the tensions between Ukrainians and Russians first-hand, I was convinced Russia would not invade – I could not see the logic (maybe strongmen don’t use logic). I hope I am also wrong about the Three Reunifications Scenario. Unfortunately, I can see the logic in it from a Chinese perspective.
The current Manufacturing View:
Although not all companies have all manufacturing in their legal jurisdiction, it is the exception rather than the rule.
The distribution of semiconductor Property, Plant, and Equipment (PPE) gives a good overview of the manufacturing capacity from a geographic perspective. Chinese privately (state) owned companies are adding an estimated 35B$. These companies specialise in Memory, Micro, CPU, and mobile semiconductors.
While PPE includes other assets, these are very small for a Semiconductor Manufacturing Company. The Fabs and equipment dominate PPE. It can also be argued that PPE is higher per dollar of revenue in the US than in China and that advanced manufacturing takes more PPE value. These are all fair arguments to consider. Still, PPE is a much more solid number than most in the industry.
We divide manufacturing capacity into three categories:
Integrated Device Manufacturing (IDM)
Semiconductor Foundry
Mixed Manufacturing
Traditionally, all semiconductor companies were IDMs that manufactured and sold branded products. With the emergence of TSMC, companies could choose to outsource manufacturing and go fabless. Some companies have chosen the mixed model and retained some manufacturing capacity while outsourcing the rest.
Property, Plant and Equipment $M, by Country of Incorporation, March 31st, 2024
The USA is still dominant despite some US capacity in other jurisdictions, so the physical location is elsewhere. Intel has Fabs in Ireland, Israel, and Malaysia, but most of its capacity is in the US. From a PPE perspective, Intel is not getting as much value from its manufacturing assets as TSMC is. This is a function of Intel making subpar manufacturing decisions, excluding Deep UV equipment. Despite these discrepancies, we still believe that a PPE analysis is solid and a source of good insights.
The PPE analysis shows that most of the chip manufacturing capacity is concentrated around the East China Sea, and 50% is in potential “Reunification” zones.
China’s 12% share of global PPE might sound low, but it is growing incredibly. Despite the US lead embargo, China still buys nearly half of the Western semiconductor tools sold, amounting to a roughly 31B$ annual run rate plus an additional 4B$ of Chinese tools. The embargo and Chips Act only accelerated this development.
The total Chinese PPE is projected to pass 100B$ within a year with these numbers. A near 50% growth will give China an estimated 18% global capacity.
If the semiconductor manufacturing capacity of South Korea and Taiwan is excluded, China will have a third of the global capacity by the end of the year. For every year that passes, China will gain more capacity than even the US.
With the exclusion, the total capacity, based on PPE, will decline from 550B$ to 300B$
Revenue versus Capacity
As global semiconductor revenue has been an average of $550B over the last couple of years, and the combined PPE is also around 550B$, it can be assumed that 1$ of PPE can generate 1$ of annual revenue. This might be too crude for accounts, but it can be used for this scenario.
Excluding Taiwanese and South Korean manufacturing, the world would be set back 15 years from a manufacturing standpoint. China would command 1/3rd of the capacity at the end of this year. This share would grow significantly every year any military action is delayed. Time is on China’s side.
How this will be devastating to the US
Based on the PPE analysis, the US would be a significant winner in the Three Reunifications Scenario, but there are some complications. The first is that the US capacity is concentrated in one company, Intel, which is not in the best of shapes. As with the other US semiconductor companies, Intel’s business heavily depends on the supply chain in Asia, especially the high-tech supply chain of Taiwan, Korea and Japan.
The destruction of the Semiconductor Supply Chain
The destruction will not only impact semiconductor manufacturing but also the semiconductor supply chain. A Korean conflict could impact US manufacturing positively, while the supply chain implications are minimal. A Taiwanese conflict, however, would be negative for the US. For the large US fabless companies it would be catastrophic and US rely a lot on the high tech Taiwanese supply chain.
The smaller and more sheltered Japanese and European Semiconductor industries are more sheltered and self-sufficient from a supply chain perspective and would likely fare better than the US.
Excluding Taiwanese and South Korean manufacturing, the world would be set back 15 years from a manufacturing standpoint. China would command 1/3rd of the capacity at the end of this year. This share would grow significantly every year any military action is delayed. Time is on China’s side.
How this will be devastating to the US
Based on the PPE analysis, the US would be a significant winner in the Three Reunifications Scenario, but there are some complications. The first is that the US capacity is concentrated in one company, Intel, which is not in the best of shapes. As with the other US semiconductor companies, Intel’s business heavily depends on the supply chain in Asia, especially the high-tech supply chain of Taiwan, Korea and Japan.
The destruction of the Semiconductor Supply Chain
The destruction will not only impact semiconductor manufacturing but also the semiconductor supply chain. A Korean conflict could impact US manufacturing positively, while the supply chain implications are minimal. A Taiwanese conflict, however, would be negative for the US. For the large US fabless companies it would be catastrophic and US rely a lot on the high tech Taiwanese supply chain.
The smaller and more sheltered Japanese and European Semiconductor industries are more sheltered and self-sufficient from a supply chain perspective and would likely fare better than the US.
China, however, would emerge as the winner. The Chinese semiconductor industry follows the deep tradition of locally building the entire supply chain. From raw goods to finished products.
As semiconductor materials manufacturing is not as PPE intensive as semiconductor manufacturing, it is more relevant to look at revenue:
According to SEMI research, in 2023, more than 35% of all Semiconductor materials outside Taiwan and South Korea will be in China.
Taking out most of the leading-edge manufacturing and supply chain would leave the Chinese semiconductor industry in the sweet spot, ready to serve the world. As the Chinese are experts in value chains, they are not likely to sell their semiconductors directly to the West, but they will be more than happy to sell them wrapped in products. Your next electronic products—phones, PCs, and Cars—might be Chinese, but you must wait until AI is back on the agenda, as the Semiconductor clock has reversed a few years.
It would serve many of Xi’s goals, including reunification, however ugly. An external enemy could be potentially humiliated by non-intervention. China is emerging as the number one country in semiconductors (based on mature nodes turned leading edge), with most of the high-tech manufacturing in the world.
As I started by saying: Fortunately, this is just a scenario….
At the VLSI Technology Symposium this week Intel released details on their i3 process. Over the last four nodes Intel has had an interesting process progression. In 2019, 10nm finally entered production with both high performance and high-density standard cells. 10nm went through several iterations eventually resulting in i7, a high-performance cell only process. When we characterize process density, we always talk about the highest density logic standard cell, 10nm achieved just over 100 million transistors per millimeter squared density (MTx/mm2), i7 in in 2022 only achieved approximately 64 MTx/mm2 density because it only had high performance cells. i4 entered production in 2023 and is once again a high-performance cell only process and achieves approximately 130 MTx/mm2. Finally, i3 will enter production in 2024 on multiple Intel products providing both high performance and high-density cells. The high-density cells achieve approximately 148 MTx/mm2 transistor density.
The key dimensions for the processes are compared in figure 1.
Figure 1. Process Key Dimensions Comparison.
In figure 1 the values for 10nm and i7 are actual values measured by TechInsights on production parts, the i4 and i3 values are from the VLSI Technology papers on i4 [1], and i3 [2]. The cell height for i3 of 210nm is for high density cells, there is also a 240nm height high performance cell with the same density as the i4 process. 240nm height high performance cells are 3 fin devices the same at i4 and the 210nm high density cells are 2 fin devices with wide metal zero.
Figure 2 presents the density changes between the processes in graphics form.
From 32nm through 10nm Intel accelerated from 2.0x to 2.4x and then to 2.7x density improvements, but as is the case with other companies pushing the leading edge, i3 is a less than 2x density jump.
Figure 2. Intel Process Density Comparison.
Figure 3 is from the Intel presentation and presents more details on the i4 to i3 process shrink.
Figure 3. i4 to i3 Process Shrink.
The i3 process will offer multiple variants targeted at different applications.
i3 base process and i3-T with TSVs targeted at client, server and base die for chiplet applications.
i3-E offer native 1.2 volt I/O devices, deep N-wells, and long channel analog devices, and is targeted at chipsets and storage applications.
i3-PT targets high performance computing and AI with 9μm pitch TSVs and hybrid bonding.
Figure 4 summarizes the process variants.
Figure 4. i3 Process Variants.
i3 features:
Smaller M2 pitch than i4.
Better fin profile.
Utilizes dipoles to set threshold voltages, i4 does not use dipoles. Dipoles improve gate oxide reliability.
Offer 14, 18, and 21 metal layer options (counts include metal 0).
4 threshold voltages, V:VT, LVT, SVT, HVT.
Contact optimization to provide less overlap capacitance.
More effective EUV usage, i4 was Intel’s first EUV process, i3 EUV processes are less complex.
Lower line resistance and capacitance than i4.
5x lower leakage at the same drive current as i4.
Increased frequency and drive current with no hot carrier increase.
Interconnect delay is now approximately half of overall delay and the base process has better RC delay, the PT process is even better.
At the same power i3 HD cells provide 18% better performance than i4 HP cells.
Figure 5 presents the interconnect pitches for the 14, 18, and 21 metal options.
Figure 5. Interconnect Pitches.
Figure 6 illustrates the improvement in interconnect RC delay.
Figure 6. Interconnect RC Delay.
And finally, figure 7 illustrates the 18% performance improvement over i4.
Figure 7. Interconnect Delay Improvement.
During an analysts briefing session questions and answers session Intel disclosed the channels are all silicon, no silicon germanium channels. Also, i4 designs have been ported to i3 and they are seeing PPA improvements on the same designs.
i3 is currently in high volume manufacturing with multiple Intel products.
i3 clearly represents a significant improvement over i4.
Comparisons to competitors
i3 is a significant improvement over i4 but how does it compare to competitors?
TechInsights has analyzed density, performance, and cost of i3 versus Samsung and TSMC processes. That analysis is available in the TechInsights platform here (free registration required):
Conclusion
Intel’s i3 process is a significant step forward from Intel’s i4 process with better density and performance. Intel’s i3 process is a more competitive foundry process than previous generations. Cost is more in-line with other foundry processes, density is slightly lower than Samsung 3nm and much lower than TSMC 3nm, but it has the best performance of the “3nm” processes.
The TSMC Technology Symposium provides a worldwide stage for TSMC to showcase its advanced technology impact and the extensive ecosystem that is part of the company’s vast reach. These events occur around the world and the schedule is winding down. TSMC covers many topics at its Technology Symposium, including industry-leading HPC, smartphone, IoT, and automotive platform solutions, 5nm, 4nm, 3nm, 2nm processes, ultra-low power, RF, embedded memory, power management, sensor technologies, and AI enablement. Capacity expansion and green manufacturing achievements were also discussed, along with TSMC’s Open Innovation Platform® ecosystem. These represent significant achievements for sure. For this post, I’d like to focus on another set of significant achievements in advanced packaging. This work has substantial implications for the future of the semiconductor industry. Let’s examine how TSMC advanced packaging overcomes the complexities of multi-die design.
Why Advanced Packaging is Important
Advanced packaging is a relatively new addition to the pure-play foundry model. It wasn’t all that long ago that packaging was a not-so-glamorous finishing requirement for a chip design that was outsourced to third parties. The design work was done by package engineers who got the final design thrown over the wall to fit into one of the standard package configurations. Today, package engineers are the rock stars of the design team. These folks are involved at the very beginning of the design and apply exotic materials and analysis tools to the project. The project isn’t real until the package engineer signs off that the design can indeed be assembled.
With this part of the design process becoming so critically important (and difficult) it’s no surprise that TSMC and other foundries stepped up to the challenge and made it part of the overall set of services provided. The driver for all this change can be traced back to three words: exponential complexity increase. For many years, exponential complexity increase was delivered by Moore’s Law in the form of larger and larger monolithic chips. Today, it takes more effort and cost to get to the next process node and when you finally get there the improvement isn’t as dramatic as it once was. On top of that, the size of new designs is so huge that it can’t fit on a single chip.
These trends have catalyzed a new era of exponential complexity increase, one that relies on heterogeneous integration of multiple dies (or chiplets) in a single package, and that has created the incredible focus and importance of advanced packaging as critical enabling technology. TSMC summarizes these trends nicely in the diagram below.
TSMC’s Advanced Packaging Technologies
TSMC presented many parts of its strategy to support advanced packaging and open the new era of heterogenous integration. These are the technology building blocks for TSMC’s 3DFabric™ Technology Portfolio:
CoWoS®: Chip-on-Wafer-on-Substrate is a 2.5D wafer-level multi-chip packaging technology that incorporates multiple dies side-by-side on a silicon interposer to achieve better interconnect density and performance. Individual chips are bonded through micro-bumps on a silicon interposer forming a chip-on-wafer (CoW).
InFO: Integrated Fan-Out wafer level packaging is a wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance. The InFO platform offers various package schemes in 2D and 3D that are optimized for specific applications.
TSMC-SoIC®: Is a service platform that provides front-end, 3D inter-chip (3D IC) stacking technologies for re-integration of chiplets partitioned from a system on chip (SoC). The resulting integrated chip outperforms the original SoC in system performance. It also affords the flexibility to integrate additional system functionalities. The platform is fully compatible with CoWoS and InFO, offering a powerful “3Dx3D” system-level solution.
The figure below summarizes how the pieces fit together.
Getting all this to work across the ecosystem requires collaboration. To that end, TSMC has established the 3DFabric Alliance to enable work with 21 industry partners to cover memory, substrate, testing and OSAT collaborations to lower 3DIC design barriers, improve STCO and accelerate 3DIC adoption. The group also drives 3DIC development in tools, flows, IP, and interoperability for the entire 3Dfabric stack. The figure below summarizes the group of organizations that are involved in this work.
There is so much effort going on to support advanced packaging at TSMC. I will conclude with one more example of this work. 3Dblox™ is a standard new language that will help make designing 3D ICs much easier. TSMC created 3Dblox alongside its EDA partners such as Ansys, Cadence, Intel, Siemens, and Synopsys to unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The figure below shows the progress that has been achieved with this effort.
3Dblox Roadmap
To Learn More
I have touched on only some of the great work going on at TSMC to create advanced packaging solutions to pave the way for the next era of multi-die, heterogeneous design. You can get more information about this important effort at TSMC here. And that’s how TSMC advanced packaging overcomes the complexities of multi-die design.
On April 25, 2024, the U.S. Department of Commerce announced the fourth, and most likely final, grant under the current U.S. CHIPS Act for leading-edge semiconductor manufacturing. With a Preliminary Memorandum of Terms (or PMT) valued at $6.14B, Micron Technologies joined the ranks of Intel Corporation, TSMC, and Samsung, each of which is slated to receive between $6.4 and $8.5B in grants to build semiconductor manufacturing capacity in the United States. Together, these four allotments total $27.64B, just shy of the $28B that Secretary of Commerce Gina Raimondo announced would be allocated to leading-edge manufacturing under the U.S. CHIPS Act. The Secretary of Commerce has stated ambitions to increase America’s global share in leading-edge logic manufacturing to 20% by the end of the decade, starting from the nation’s current position at 0%. But will the $27.64B worth of subsidies be enough to achieve this lofty goal?
To track achievement toward the 20% goal, one needs both a numerator and a denominator. The denominator consists of global leading edge logic manufacturing while the numerator is limited to leading edge logic manufacturing in the United States. Over the next decade, both the numerator and the denominator will be subject to large-scale changes, making neither figure easy to predict. For nearly half a century, the pace of Moore’s Law’s has placed the term “leading-edge” in constant flux, making it difficult to determine which process technology will be considered leading-edge in five years’ time. More recently, American chip manufacturing must keep pace with foreign development, as numerous countries are also racing to onshore leading-edge manufacturing. These two moving targets make it difficult to measure progress toward Secretary Raimondo’s stated goal and warrant a closer examination of the potential challenges faced.
Challenge #1: Defining Leading Edge and Success Metrics
The dynamic nature of Moore’s Law, which predicts the number of transistors on a chip will roughly double every two years (while holding costs constant), leads to a steady stream of innovation and rapid development of new process technologies. Consider TSMC’s progression over the past decade. In 2014, it was the first company to produce 20 nm technology at high volume production. Now, in 2024, the company is mass producing logic technology within the 3 nm scale. Intel, by comparison, is currently mass producing its Intel 4. (In 2021, Intel renamed its Intel 7nm processors to Intel 4.)
Today, the definition of advanced technologies and leading edge remains murky at best. As recently as 2023, TSMC’s Annual Report identified anything smaller than 16 nm as leading edge. A recent Trend Force report used 16 nm as the dividing line between “advanced nodes” and mature nodes. Trend Force predicts that U.S. manufacturing of advanced nodes will grow from 12.2% to 17% between 2023 and 2027, while Secretary Raimondo declared “leading-edge” manufacturing will grow from 0% to 20% by 2030. This lack of clarity dates back to the 2020 Semiconductor Industry Association (“SIA”) study which served as the impetus for the U.S. CHIPS Act. The 2020 SIA report concluded that U.S. chip production dropped from 37% to 10% between 1999 and 2019 based upon total U.S. chip manufacturing data. To stoke U.S. fears of lost manufacturing leadership, it pointed to the fast-paced growth of new chip factories in China, though none of these would be considered leading-edge under any definition.
A new 2024 report by the SIA and the Boston Consulting Group on semiconductor supply chain resilience further muddies the waters by shifting the metrics surrounding the advanced technologies discourse. It defines semiconductors within the 10 nm scope as “advanced logic” and forecasts that the United States’ position in advanced logic will increase from 0% in 2022 to 28% by 2032. It also predicts that the definition of “leading-edge” will encompass technologies newer than 3 nm by 2030 but fails to provide any projection of the United States’ position within the sub3 nm space. This begs the question: Should Raimondo’s ambition to reach 20% in leading edge be evaluated under the scope of what is now considered as “advanced logic”, or should the standard be held to a more rigorous definition of “leading edge”? As seen within the report, U.S. manufacturing will reach the 20% goal by a comfortable margin if “advanced logic” is used as the basis for evaluation. Yet, the 20% goal may be harder to achieve if one were to hold the stricter notion of “leading edge”.
Figure #2, Data taken from NIST
The most current Notice of Funding Opportunity under the U.S. CHIPS Act defines leading-edge logic as 5 nm and below. Many of the CHIPS Act logic incentives are for projects at the 4 nm and 3 nm level, which presumably meet today’s definition of leading-edge. Intel has announced plans to build one 20A and one 18A factory in Arizona, two leading edge factories in Ohio, bring the latest High NA EUV lithography to its Oregon research and development factory, and expand its advanced packaging in New Mexico. TSMC announced it will use its incentives for 4 nm FinFet, 3 nm, and 2 nm but fails to identify how much capacity will be allocated to each. Similarly, Samsung revealed its plans to build 4nm and 2 nm, as well as advanced packaging, with its CHIPS Act funding. Like TSMC, Samsung has not shared the volume production it expects at each node. However, by the time TSMC’s and Samsung’s 4 nm projects are complete, it’s unlikely they will be considered leading-edge by industry standards. TSMC is already producing 3 nm chips in volume and is expected to reach high volume manufacturing of 2 nm technologies in the next year. Both Intel and TSMC are predicting high volume manufacturing of sub-2nm by the end of the decade. In addition, the Taiwanese government has ambitions to break through to 1 nm by the end of the decade, which may lead to an even narrower criterion for “leading-edge.”
In this way, the United States’ success will be contingent on the pace of developments within the industry. So far, the CHIPS Act allocations for leading-edge manufacturing are slated to contribute to two fabrication facilities producing at 4 nm, and six at 2 nm or lower. If “leading-edge” were to narrow down to 3 nm technologies by 2030 as predicted, roughly a fourth of the fabrication facilities built for leading-edge manufacturing will not contribute to the United States’ overall leading-edge capacity.
If the notion of “leading-edge” shrinks further, even fewer fabrication facilities will be counted towards the United States’ leading-edge capacity. For instance, if the Taiwanese government proves to be successful with its 1 nm breakthrough, it would cast further doubt on the validity of even a 2 nm definition for “leading-edge”. Under such circumstances, the Taiwanese government will not only be chasing a moving target, but will shift the goalpost for the rest of the industry in the process, greatly complicating American efforts to reach the 20% mark. Thus, it becomes essential for the American leadership to keep track of foreign developments within the manufacturing space while developing its own.
Challenge # 2: Growth in the United States Must Outpace Foreign Development
Any measure of the success of the CHIPS Act must consider not only the output of leading edge fabrication facilities built in the United States, but also the growth of new fabs outside the United States. Specifically, to boost its global share of leading edge capacity by 20%, the U.S. must not only match the pace of its foreign competition, it must outpace it.
This means the U.S. must contend with Asia, where government subsidies and accommodating regulatory environments have boosted fabrication innovation for decades. Though Asian manufacturing companies will contribute to the increase of American chipmaking capabilities, it appears most chipmaking capacities will remain in Asia through at least 2030. For instance, while TSMC’s first two fabrication facilities in Arizona can produce a combined output of 50,000 wafers a month, TSMC currently operates 4 fabrication facilities in Taiwan that can each produce up to 100,000 wafers a month. Moreover, Taiwanese companies have announced plans to set up 7 additional fabrication facilities on the island, 2 of which include TSMC’s 2 nm facilities. In South Korea, the president has unveiled plans to build 16 new fabrication facilities through 2047 with a total investment of $471 billion, establishing a fabrication mega-cluster in the process. The mega-cluster will include contributions by Samsung, suggesting expansion of Korea’s leading-edge capacity. Even Japan, which has not been home to logic fabrication in recent years, has taken steps to establish its leading-edge capabilities. The Japanese government is currently working with the startup Rapidus to initiate production for 2 nm chips, with plans of a 2 nm and 1 nm fabrication facility under way. While the U.S. has taken a decisive step to initiate chipmaking, governments in Asia are also organizing efforts to establish or maintain their lead.
Asia is not the only region growing its capacity for leading edge chip manufacturing. The growth of semiconductor manufacturing within the E.U. may further complicate American efforts to increase its leading-edge shares by 20%. The European Union recently approved of the E.U. Chips Act, a $47B package that aims to bring the E.U.’s global semiconductor shares to 20% by 2030. Already, both Intel and TSMC have committed to expanding semiconductor manufacturing in Europe. In Magdeburg, Germany, Intel seeks to build a fabrication facility that uses post-18A process technologies, producing semiconductors within the order of 1.5 nm. TSMC, on the other hand, plans to build a fabrication facility in Dresden, producing 12/16 nm technologies. Though the Dresden facility may not be considered leading-edge, TSMC’s involvement could lead to more leading-edge investments within European borders in the near future.
In addition to monetary funding under the CHIPS Act, the U.S. also faces non-monetary obstacles that may hamper its success. TSMC’s construction difficulties in Arizona have been well-documented and contrasted with the company’s brief and successful construction process in Kumamoto, Japan. Like TSMC, Intel’s U.S. construction in Ohio has also faced setbacks and delays. According to the Center for Security and Emerging Technology, many countries in Asia provide infrastructure support, easing regulations in order to accelerate the logistical and utilities-based processes. For instance, during Micron’s expansion within Taiwanese borders, the Taiwanese investment authority assisted the company with land acquisition and lessened the administrative burden the company had to undergo for its construction. The longer periods required to obtain regulatory approvals and complete construction in the U.S. provide other nations with significant lead time to outpace U.S. growth.
Furthermore, the monetary benefits of CHIPS Act rewards will take time to materialize. Despite headlines claiming CHIPS Act grants have been awarded, no actual awards have been issued. Instead, Intel, TSMC, Samsung and Micron have received Preliminary Memorandum of Terms, which are not binding obligations. They are the beginning of a lengthy due diligence process. Each recipient must negotiate a long-form term sheet and, based upon the amount of funding per project, may need to obtain congressional approval. As part of due diligence, funding recipients may also be required to complete environmental assessments and obtain government permits. Government permits for semiconductor factories can take 12- 18 months to obtain. Environmental assessments can take longer. For example, the average completion and review period for an environmental impact statement under the National Environmental Policy Act is 4.5 years. Despite the recent announcements of preliminary terms, the path to actual term sheets and funding will take time to complete.
Even if the due diligence and term sheets are expeditiously completed, the recipients still face years of construction. The Department of Commerce estimates a leading-edge fab takes 3-5 years to construct after the approval and design phase is complete. Moreover, two of the four chip manufacturers have already announced delays in construction projects covered by CHIPS Act incentives. Accounting for 2-3 years to obtain permits and complete due diligence, 3-5 years for new construction, and an additional year of delay, it may be 6-9 years before any new fabs begin production. To achieve the CHIPS Act goal of 20% by 2030, the United States must do more than provide funding– it must ensure the due diligence and permitting processes are streamlined to remain competitive with Europe and Asia.
The Future of Leading-Edge in the United States
Between the constant changes in the meaning of “leading-edge” under Moore’s Law and the growing presence of foreign competition within the semiconductor industry, the recent grant announcements of nearly $28B for leading-edge manufacturing are only the start of the journey. The real test for the U.S. CHIPS Act will occur over the next few years, when the CHIPS Office must do more than monitor semiconductor progress within the U.S. It must also facilitate timely completion of the CHIPS Act projects and measure their competitiveness as compared to overseas expansions. The Department of Commerce must continually evaluate whether its goals still align with developments in the global semiconductor industry.
As such, whether the United States proves successful largely depends on why achieving the 20% target matters. Is the goal to establish a steady supply of advanced logic manufacturing to protect against foreign supply-side shocks, or is it to take and maintain technological leadership against the advancements of East Asia? If the former case, then abiding to the notion of “advanced logic” will suffice; the degree of such an achievement will be smaller compared to what was initially promised under “leading-edge”, but it remains a measured and sensible goal for the U.S. to achieve. If the latter case holds true, achieving the 20% benchmark would place the United States in a much stronger position within the global supply chain. To do so, however, will undoubtedly require much greater funding efforts towards leading-edge than the $28B that has been allocated.
National governments are increasingly investing efforts to establish a stronger productive capacity for semiconductors, and many will continue to do so in the succeeding decades. If the United States aims to keep pace with the rest of the industry, then it must maintain a steady stream of support towards leading-edge technologies. It will be an expensive initiative, but some leading figures such as Secretary Raimondo are already suggesting a secondary CHIPS Act to expand upon its initial efforts; In the global race, another subsidy package will provide the nation with a much needed push towards the 20% finish line. Hence, despite all the murkiness surrounding the United States’s fate within the semiconductor industry, one fact remains certain: the completion of the CHIPS Act should not be seen as the conclusion, but as the prologue to America’s chipmaking future.
This article previews Nvidia’s earnings release and will be updated during and after the earnings release. As usual, we will compare and contrast the Nvidia earnings with our supply chain glasses to identify changes and derive insights. Please return to this article, as it will be updated over the next week as we progress with our analysis.
After three insane quarters, Nvidia’s guidance suggests that this quarter will be calmer. I am not sure the stock market can handle growth rates like Nvidia is enjoying once more without going insane. The analysts’ consensus is slightly above Nvidia’s at $24.6B. Our survey shows that the industry expectations are somewhat more optimistic.
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From humble beginnings as a graphics company adored by hardcore gamers only, Nvidia is now the undisputed industry champion and has made the industry famous far beyond us wafer nerds.
When people hear you are in the semiconductor industry, they want to know what you think of Nvidia’s stock price (which is insane but could be even more insane). Obviously, this is driven by the irresistible hunger for AI in the data centre, but this is not our expertise (we recommend Michael Spensers: AI Supremacy for that). We will also refrain from commenting on stock prices and concentrate on the business and supply chain side of the story.
The supply chain has already created a frenzy amongst analysts as TSMC reported April Revenue up almost 60%. Our analysis of the TSMC revenue numbers aligned to an April quarter end shows that the TSMC trend is relatively flat and does not reveal much about Nvidia’s numbers. However, TSMC’s revenue numbers do not have to change much for Nvidia’s numbers to skyrocket. The value is not in the silicon right now as we will be diving into later.
The golden goose
The most important market for Nvidia is the data center and its sky-high demand for AI servers. Over the last couple of years, Nvidia and AMD have been chipping away at Intel’s market share until three quarters ago, when Nvidia’s Datacenter business skyrocketed and sucked all value out of the market for the other players. Last quarter Nvidia capture over 87% of all operating profit in the processing market.
This has faced in particular Intel with a nasty dilemma:
Nvidia has eaten Intel’s lunch.
Intel has recently unveiled a bold and promising strategy, a testament to its resilience and determination. However, this strategy comes with significant financial challenges. As illustrated in the comparison below, Intel has historically been able to fund its approximately $4B/qtr Capex as its Operating profits hovered around $11B. But as the market changed, Intel’s operating profit is now approaching zero while its CapEx spending is increasing as a result of the new strategy of also becoming a foundry ased to the area of $6B$/qtr. The increased spending is now approximately $6M and is not a temporary situation but a reality that will persist
Intel can no longer finance its strategy through retained earnings and must engage with the investor community to obtain financing. Intel is no longer the master of its destiny.
Intel is hit by two trends in the Datacenter market:
The transition from CPU to GPU
The transition from Components to Systems.
Not only did Intel miss the GPU transition business, but it also lost the CPU business because of the system transition. Nvidia GPU systems will use their CPUs, Intel is not invited.
The revolution of the semiconductor supply chain
There are two main reasons the AI revolution is changing the data center part of the supply chain.
One is related to the change from standard packaged DRAM to High-Bandwidth Memory (HBM), and the other is related to new packaging technologies (CoWoS by TSMC). Both are related and caused by the need for bandwidth. As the GPU’s computational power increases, it must have faster memory access to deliver the computational advantage needed. The memory needs to be closer to the GPU and more of it, a lot more.
A simplified view of the relevant packaging technologies can be seen below:
The more traditional packaging method (2D) involves mounting the die on a substrate and connecting the pads with bond wires. 2.3D technology can bring the chips closer by flipping them around and mounting them on an interposer (often Silicon).
The current NVIDIA GPUs are made with 2.5D technology. The GPUs are flanked by stacks of DRAM die controlled by a base Memory Logic Die.
3D technology will bring memory to the top of the GPU and introduce many new problems for intelligent semiconductor people to solve.
This new technology is dramatically changing the supply chain. In the traditional model standard of the rest of the industry, the server card manufacturer procured all components from the suppliers individually.
The competition between the Processing, Memory and the Server companies kept pricing in check for the cloud companies.
Much has become more complex in the new AI server supply chain, as seen below.
The processing company is now in control of the supply chain. With Nvidia’s volumes, supply becomes very important, and as all of the technologies and components are leading-edge, the supply can be unstable. Memory companies need dies from foundries and will negotiate and deliver directly to the processing companies. That Nvidia is in control can be seen in their incredible margins.
This change again makes the Semiconductor supply chain more complex, but complexity is our friend.
What did Nvidia report, and what does it mean?
Nvidia posted $26B$ revenue, significantly above guidance and below the $27.5B we believed was the current capacity limit. It looked like Nvidia could squeeze the suppliers to perform at the maximum.
The result was a new record in the Semiconductor industry. Back in ancient history (last year), only Intel and Samsung could break quarterly records, as can be seen below.
Nvidia also disclosed their networking revenue for the first time, through the earlier calls we had a good idea of the size but now it is confirmed.
As we believe almost all of the networking revenue is in the data center category, we expected it to grow as the processing business but networking revenue was down down just under 5% quarterly suggesting the bill of material is shifting in the AI server products.
Even though the networking revenue was down, the growth from same quarter last year was up, making Nvidia the fastest growing networking company in the industry. More about that later.
The most important market for Nvidia is the data center processing market and its rapid uncontrolled disassembly of the old market structure. From being a wholly owned subsidiary of Intel back in 2019, the painful story unfolds below.
In Q1-2024, Nvidia generated more additional processing revenue in the data center than Intel’s total revenue. From an operating profit perspective, Nvidia had an 87% market share and delivered a new record higher than the combined operating profit in Q1-24.
Although Nvidia reported flat networking revenue, the company’s dominance is spreading to Data center networking. Packaging networking into server systems ensures that the networking components are not up for individual negotiation and hurts Nvidia’s networking competitors. It also provides an extraordinary margin.
We have not yet found out what is behind the drop in networking, but it is likely a configuration change in the server systems or a change in categorization inside Nvidia.
Nvidia declared a 10-1 stock split.
Claus Aasholm @siliconomy Spending my time dissecting the state of the semiconductor industry and the semiconductor supply chain. “Your future might be somebody else’s past.”
AMD’s Q1-2024 financial results are out, prompting us to delve into the Data Center Processing market. This analysis, usually reserved for us Semiconductor aficionados, has taken on a new dimension. The rise of AI products, now the gold standard for semiconductor companies, has sparked a revolution in the industry, making this analysis relevant to all.
Jenson Huang of Nvidia is called the “Taylor Swift of Semiconductors” and just appeared on CBS 60 Minutes. He found time for this between autographing Nvidia AI Systems and suppliers’ memory products.
Lisa Su of AMD, who has turned the company’s fate, is now one of only 26 self-made female billionaires in the US. Later, she was the CEO of the year in Chief Executive Magazine and has been on the cover of Forbes magazine. Lisa Su still needs to be famous in Formula 1
Hock Tan of Broadcom, desperately trying to avoid critical questions about the change of WMware licensing, would rather discuss the company’s strides in AI accelerator products for the Data Center, which has been significant.
An honorable mention goes to Pat Gelsinger of Intel, the former owner of the Data Center processing market. He has relentlessly been in the media and on stage, explaining the new Intel strategy and his faith in the new course. He has been brutally honest about Intel’s problems and the monumental challenges ahead. We deeply respect this refreshing approach but also deal with the facts. The facts do not look good for Intel.
AMD’s reporting
While the AMD result was challenging from a corporate perspective, the Data Center business, the topic of this article, did better than the other divisions.
The gaming division took a significant decline, leaving the Data Center business as the sole division likely to deliver robust growth in the future. As can be seen, the Data Center business delivered a solid operating profit. Still, it was insufficient to take a larger share of the overall profit in the Data Center Processing market. The 500-pound gorilla in the AI jungle is not challenged yet.
The Data Center Processing Market
Nvidia’s Q1 numbers have been known for a while (our method is to allocate all of the quarterly revenue in the quarter of the last fiscal month), together with Broadcom’s, the newest entry into the AI processing market. With Intel and AMD’s results, the Q1 overview of the market can be made:
Despite a lower growth rate in Q1-24, Nvidia kept gaining market share, keeping the other players away from the table. Nvidas’ Data Center Processing market share increased from 66.5% to 73.0% of revenue. In comparison, the share of Operating profit declined from 88.4% to 87.8% as Intel managed to get better operating profits from their declining revenue in Q1-24.
Intel has decided to stop hunting low-margin businesses while AMD and Broadcom maintain reasonable margins.
As good consultants, we are never surprised by any development in our area once presented with numbers. That will not stop us from diving deeper into the Data Center Processing supply chain. This is where all energy in the Semiconductor market is concentrated right now.
The Supply Chain view of the Data Center Processing
A CEO I used to work for used to remind me: “When we discuss facts, we are all equal, but when we start talking about opinions, mine is a hell of a lot bigger than yours.”
Our consultancy is built on a foundation of not just knowing what is happening but also being able to demonstrate it. We believe in fostering discussions around facts rather than imposing our views on customers. Once the facts are established, the strategic starting point becomes apparent, leading to more informed decisions.
“There is nothing more deceptive than an obvious fact.” Sherlock Homes
Our preferred tool of analysis is our Semiconductor Market model, seen below:
The model has several different categories that have proven helpful for our analysis and are described in more detail here:
We use a submodel to investigate the Data Center supply chain. This is also an effective way of presenting our data and insights (the “Rainbow” supply and demand indicators) and adding our interpretations as text. Our interpretations can undoubtedly be challenged, but we are okay with that.
Our current findings that the supply chain is struggling to get sufficient CoWoS packaging technology and High Bandwith Memory is not a controversial view and is shared by most that follow the Semiconductor Industry.
This will not stop us from taking a deeper dive to be able to demonstrate what is going on.
The Rainbow bars between the different elements in the supply chain represent the current status.
The interface between Materials & Foundry shows that the supply is high, while the demand from TSMC and other foundries is relatively low.
Materials situation
This supply/demand situation should create a higher inventory position until the two bars align again in a new equilibrium. The materials inventory index does show elevated inventory, and the materials markets are likely some distance away from recovery.
Semiconductor Tools
The recent results of the semiconductor tools companies show that revenues are going down, and the appetite of IDMs and foundries indicates that the investment alike is saturated. The combined result can be seen below, along with essential semiconductor events:
The tools market has flatlined since the Chips Act was signed, and there can certainly be a causal effect (something we will investigate in a future post). Even though many new factories are under construction, these activities have not yet affected the tools market.
A similar view of the subcategory of logic tools which TSMC uses shows an even more depressed revenue situation. The tools revenue is back to a level of late 2021, in a time with unprecedented expansion of the semiconductor manufacturing foot print:
This situation is confirmed on the demand side as seen in the TSMC Capital Investments chart below.
Right after the Chips Act was signed, TSMC lowered the capex spend to close to half, making life difficult for the tools manufacturers.
The tools foundry interface has high supply and low demand as could be seen in the supply chain model. The tools vendors are not the limiting factor of GPU AI systems.
The Foundry/Fabless interface
To investigate the supply demand situation between TSMC and it’s main customers we choose to select AMD and Nvidia as they have the simplest relationship with TSMC as the bulk of their business is processors made by TSMC.
The inventory situation of the 3 companies can be seen below.
As TSMC’s inventory is building up slightly does not indicate a supply problem however this is TSMC total so their could be other moving parts. The Nvidia peak aligns with the introduction of the H100.
TSMC’s HPC revenue aligns with the Cost of Goods sold of AMD and Nvidia.
As should be expected, these is no surpises in this view. As TSMC’s HPC revenue is growing faster than the COGS of Nvidia and AMD, we can infer that a larger part of revenue is with other customers than Nvidia and AMD. This is a good indication that TSMC is not supply limited from a HPC silicon perspective. Still, the demand is still outstripping supply at the gate of the data centers.
The Memory, IDM interface
That the skyhigh demand for AI systems is supply is limited, can be seen by the wild operating profit Nvidia is enjoying right no. The supply chain of AI processors looks smooth as we saw before. This is confirmed by the TSMC’s passivity in buying new tools. If there was a production bottle neck, TSMC would have taken action from a tools perspective.
An anlysis of Memory production tools hints at the current supply problem.
The memory companies put the brakes on investments right after the last downcycle began. The last two quarters the demand has increased in anticipation of the High Bandwidth Memory needed for AI.
Hynix in their rececent investor call, confirmed that they had been underinvesting and will have to limit standard DRAM manufacturing in order to supply HBM. This is very visible in our Hynix analysis below.
Apart from the limited supply of HBM, there is also a limitation of advanced packaging capacity for AI systems. As this market is still embryonic and developing, we have not yet developed a good data method to be able to analyze it but are working on it.
While our methods does not prove everything, we can bring a lot of color to your strategy discussions should you decide to engage with our data, insights and models.
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“Real men have fabs” was an insult AMD founder Jerry Sanders hurled at his poor competitors who could not afford to build fabs. A few years later, AMD would be fabless, spinning off its manufacturing facilities as GlobalFoundries. This was the beginning of a transformative period for the industry.
Lisa Su could rightfully retort: “Real women don’t need fabs!”
Before the transformative era, all semiconductor companies were Integrated Device Manufacturers (IDM) that held the reins of designing, manufacturing, packaging, testing, and selling all their semiconductors.
Being a leader in all aspects of Semiconductor Manufacturing was becoming increasingly complex and expensive. Only a few companies had the market position and the financial strength to continue as IDMs.
The first elements to be outsourced were the backend manufacturing, the packaging and testing. It was labour-intensive and not a part of the manufacturing process that added significant economic value. First, operations were moved to Asia, and later, they were outsourced entirely as specialised companies started to appear. The Outsourced Assembly and Test (OSAT) market was born.
The IDM age was a boring time for market analysts.
The individual companies still did the front end (Wafer processing) of the Manufacturing.
In the late 1980s, the Taiwanese government offered Morris Chang, the founder of TSMC, a blank check to establish a local semiconductor industry. He had been working for Texas Instruments and observed that Japanese semiconductor factories outperformed US fabs significantly. The Japanese successfully transformed their society into a technology-based economy that would outcompete the US for over a decade.
Morris offered Intel and Texas Instruments to invest in the company, but they declined. Philips decided to trade their manufacturing technology and IP for a quarter stake in the new company, and the first foundry was born.
The increasing cost of building fabs and developing new technologies limited the number of new startups in the industry. However, new companies could enter the market with TSMC carrying the Capex cost of developing technologies and building factories. The fabless companies created a new market segment competing in design and let TSMC handle the manufacturing. In 2008, AMD gave up and became fabless themselves.
The current market structure
Since then, the Semiconductor market has become an even more complex web of submarkets and categories. This is happening as the industry has risen from an economic engine to become a matter of national security.
Understanding what happens in the semiconductor industry has never been more critical or challenging.
We continuously develop our industry model to analyse the industry and provide data and insights to our customers. This allows us to study the interfaces between the different submarkets of the value chain and detect market ripples early.
In a value chain, somebody’s future might be somebody else past.
We are not arguing that our model is correct or cannot be improved; we only know that it works for us now and that we must continue improving it.
A graphical representation of our industry model can be seen below:
The model has zones representing the different stages of the Semiconductor business. The design zone in the middle is where the design authority and absolute product ownership reside.
The manufacturing zone on the left represents front-end wafer manufacturing, and to the right is an assembly of systems by EMS or OEMs and the distribution channel, if applicable.
The brand zone is introduced as some semiconductor design owners also have a visible brand towards the end users of their products.
At the right are the end users of the Semiconductor products. We work with four different categories. The latest are large capital projects representing the large cloud and AI projects that have changed the dynamics of the industry lately.
The investment zone at the top represents what is needed to enable design and manufacturing. At the bottom, the supply zone represents the supply channels for front-end and back-end manufacturing.
We monitor the boundaries between these zones for insights that can enlighten us on what happens in the semiconductor market.
The major semiconductor business models
The industry’s most traditional business model is the integrated device manufacturer (IDM), responsible for both the design and manufacturing of the value chain.
Only the largest and most profitable companies have been able to maintain this business model due to the increasing costs of building wafer fabs. Memory companies also follow this model, as being competitive in memory is linked very closely to being competitive in manufacturing.
The rise of TSMC allowed semiconductor companies to go Fabless and outsource front-end manufacturing to foundries, concentrating on the design, sales, and marketing of semiconductor products.
A handful of companies use a mixed model, where they own their fabs and also use foundry. This Fab/Foundry model is popular amongst analogue and power companies that can operate analogue and power fabs, even though the leading edge digital manufacturing is outside their reach.
Some semiconductor customers with specialised demand are now so large that they design silicon for internal use. The Chip Designing Customers are mainly the large cloud and AI data centre-owning tech companies.
The last category is the Brand Customers. In this category, the semiconductor cannot be directly bought but is part of a system. The semiconductor inside is “branded” to the market as part of the system. Apple started this category, and the company promotes the semiconductor content of its products in its marketing. Recently, Nvidia also entered this category with its GPU-based AI systems.
There will be future categories as a result of two intertwined trends. The move from CPU to GPU requires a move from components to systems to work.
The owners of bricks
As the semiconductor sector has changed from an economically driven global industry to a politically influenced area of national security, the level of education on the market composition has deteriorated.
Because of the complexity of the industry, no good information is available about where the chips are physically made. Each chip has several countries of origin as it moves through the value chain.
Most chips are not made in Taiwan or by TSMC.
We base our research on the country of incorporation, where the political influence is most substantial and on financial Property, Plant and Equipment (PPE). Manufacturing capacity is not the same as that of PPE, but in the semiconductor industry, the most significant part of PPE is manufacturing.
Using this with our industry model, we get the following view of the distribution of PPE:
This gives a more nuanced image of what authority the properties are under rather than where they are located. This is increasingly important as governments are starting to lean on their local Semiconductor companies for patriotic investments.
In Q4-24, the most significant growth of PPE was in China, while Taiwan was declining. Europe also showed strong growth, which needs to be added to the political dialogue.
Applying our industry model gives the following output:
This is a different image than the broader press paints. From a PPE perspective, the two large IDMs with a foundry model (Intel and Samsung) dominate. The Foundry PPE is actually in decline while all other areas are growing.
The growth of the companies with mixed Fab/Foundry models is fascinating. This shows that the smaller mixed Fab/Foundry companies are adding PPE faster than the other models, a sign of them becoming more of a manufacturing company than a fabless company.
Traditionally, they have been unable to participate in the crazy manufacturing race of processing semiconductors, which they have outsourced. At the same time, these companies have manufactured analogue and power products on their fabs. While still expensive, these fabs don’t need the same insane technology as the processing parts.
The investment situation
As PPE depreciates quite fast in the Semiconductor industry, representing the rapid technological developments, the manufacturing part of the Semiconductor industry is dependent on high-octane Capital injections revealed in the cash flow statements under Capital Expenditure or Additions to PPE.
While fabless semiconductor companies can get away with a CapEx-to-revenue ratio (how much of revenue is spent on CapEx) of 3-4%, the IDMs need to shovel 28% of their income back into CapEx, as seen below.
This chart also reveals the manufacturing appetite of the mixed Fab/Foundry model companies. While Analog Devices and NXP are closer aligned with the Fabless model, Infineon and ST of Europe are pursuing more manufacturing. At the top is Texas Instruments, with a 29% Revenue to Capex Ratio in Q4-23.
TI’s recent Q1-24 result revealed that the company now has a ratio of 34%, showing a steadfast commitment to more manufacturing. The company also expect to be able to capture a $1B grant from the US Chips Act.
The Foundry investment situation
The “Most chips are made in Taiwan” story should be “Most Foundry manufacturing is in Taiwan” instead. In Q4-23, TSMC represented 62% of the revenue and 87% of the operating profits in the Foundry market, so it is undoubtedly the gold standard. (A deeper dive into the Foundry market is here.)
The CapEx to revenue ratio for the foundries can be seen below:
China foundries outspend all Others.
While the investments from the Taiwanese foundries have been high, they have been significantly outspent by the Chinese foundries. At times with CapEx that a higher than revenue, revealing the foundries operate in a different economical system than the reset. Recently also the American foundries have climbed higher and now has a CapEx to Revenue ratio slightly higher than Taiwan.
We keep monitoring the dynamics in the Semiconductor Industry using our proprietary models based on facts. If you want access to our data or neutral input to your strategy process, please contact us at: claus.aasholm@SemiBizIntel.com
NVIDIA cuLitho Accelerates Semiconductor Manufacturing’s Most Compute-Intensive Workload by 40-60x, Opens Industry to New Generative AI Algorithms.
An incredible example of semiconductor industry partnerships was revealed during the Synopsys User Group (SNUG) last month. It started with a press release but there is much more to learn here in regards to semiconductor industry dynamics.
I saw a very energized Jensen Huang, co-founder and CEO of Nvidia, at GTC which was amazing. It was more like a rock concert than a technology conference. Jensen appeared at SNUG in a much more relaxed mode chatting about the relationship between Nvidia and Synopsys. Jensen mentioned that in exchange for Synopsys software, Nvidia gave them 250,000 shares of pre IPO stock which would now be worth billions of dollars. I was around back then at the beginning of EDA, Foundries, fabless, and it was quite a common practice for start-ups to swap stock for tools.
Jensen said quite clearly that without the support of Synopsys, Nvidia would not have not gotten off the ground. He has said the same about TSMC. In fact, Jensen and TSMC founder Morris Chang are very close friends as a result of that early partnership.
The new cuLitho product has enabled a 45x speedup of curvilinear flows and a nearly 60x improvement on more traditional Manhattan-style flows. These are incredible cost savings for TSMC and TSMC’s customers and there will be more to come.
“Computational lithography is a cornerstone of chip manufacturing,” said Jensen Huang, founder and CEO of NVIDIA. “Our work on cuLitho, in partnership with TSMC and Synopsys, applies accelerated computing and generative AI to open new frontiers for semiconductor scaling.”
“Our work with NVIDIA to integrate GPU-accelerated computing in the TSMC workflow has resulted in great leaps in performance, dramatic throughput improvement, shortened cycle time and reduced power requirements,” said Dr. C.C. Wei, CEO of TSMC. “We are moving NVIDIA cuLitho into production at TSMC, leveraging this computational lithography technology to drive a critical component of semiconductor scaling.”
“For more than two decades Synopsys Proteus mask synthesis software products have been the production-proven choice for accelerating computational lithography — the most demanding workload in semiconductor manufacturing,” said Sassine Ghazi, president and CEO of Synopsys. “With the move to advanced nodes, computational lithography has dramatically increased in complexity and compute cost. Our collaboration with TSMC and NVIDIA is critical to enabling angstrom-level scaling as we pioneer advanced technologies to reduce turnaround time by orders of magnitude through the power of accelerated computing.”
“There are great innovations happening in computational lithography at the OPC software layer from Synopsys, at the CPU-GPU hardware layer from NVIDIA with the cuLitho library, and of course, we’re working closely with our common partner TSMC to optimize their OPC recipes. Collectively, we have been able to show some dramatic breakthroughs in terms of performance for one of the most compute-intensive semiconductor manufacturing workloads.” — Shankar Krishnamoorthy, GM of the Synopsys EDA Group
Collaboration and partnerships are still critical for the semiconductor industry, in fact collaborative partnerships have been a big part of my 40 year semiconductor career. TSMC is an easy example with the massive ecosystem they have built. Synopsys is in a similar position as the #1 EDA company, the #1 IP company, and the #1 TCAD company. All of the foundries closely collaborate with Synopsys, absolutely.
Throughout the debate on fab incentives and the Chips Act I keep seeing comments like; TSMC makes >90% of all advanced silicon, or sometimes Taiwan make >90% of all advanced silicon. This kind of ill-defined and grossly inaccurate statement drives me crazy. I just saw someone make that same claim in the SemiWiki forums and I decided it was time to comment on this.
Let’s start with defining what is an advanced semiconductor. Since the specific comment is about TSMC, let’s start with the TSMC definition, TSMC breaks out 7nm and below as advanced. This is a good break point in logic because Samsung and TSMC 7nm both have densities of approximately 100 million transistor per millimeter squared (MTx/mm2). Intel 10nm also has approximately 100 MTx/mm2, therefore we can count Samsung and TSMC 7nm and below and Intel 10nm and below.
That all works for logic, but this whole discussion ignores other advanced semiconductors. I would argue that there are three truly leading edge advanced semiconductors in the world today where state-of-the-art equipment is being pushed to the limits of what is achievable: 3DNAND, DRAM, and Logic. In each case there are three or more of the worlds largest semiconductor companies pushing the technology as far and as fast as humanely possible. Yes, the challenges are different, 3DNAND has relatively easy lithography requirements but deposition and etching requirements are absolutely at the edge of what is achievable. DRAM has a mixture of lithography, materials and high aspect ratio challenges. Logic has the most EUV layers and process steps but they are all equally difficult to successfully produce with good yield.
Including 3DNAND and DRAM means we need an “advanced semiconductor” limits for these two processes. When 7nm was first being introduced for logic, 3DNAND was at the 96/92 layer generation and DRAM was at 1y. We will use those as the limits for advanced semiconductors.
In order to complete this analysis without spending man-days that I don’t have to spare, I simply added up the worldwide installed capacity for 3DNAND 96/92L layers and greater, DRAM 1y and smaller and Logic 7nm (i10nm) and smaller. Furthermore I broke out logic into TSMC and other.
Figure 1 illustrates the worldwide installed capacity in percentage broken out by those categories.
Figure 1. Worldwide Advanced Silicon Installed Capacity by Category.
From figure 1 it can be seen that TSMC only represents 12% of worldwide “advanced silicon”, way off the 90% number being thrown around. Now utilization could change these numbers some and I haven’t included that due to time constraints, but I don’t think it would change this that much and as the memory sector recovers it will become a non issue.
I also looked at this a second way which is just worldwide advanced logic, see figure 2.
Figure 2. Worldwide Advanced Logic Installed Capacity by Category.
From figure 2 we can see that even when we look at Advanced Logic TSMC is only 64% versus “90%”.
The only way we would get to 90% is if we defined “advanced silicon” as 3nm logic. This would require a good definition of what 3nm logic is. On a density basis TSMC is the only 3nm logic process in the world, Samsung and Intel are really 5nm processes on a density basis, although Intel i3 is in my estimation the highest performing process available.
In conclusion, TSMC actually only makes up 12% of worldwide Advanced Silicon and only 64% of Advanced Logic. This is not to minimize the importance of TSMC to the global electronics supply chain, but when debating things as important as the worldwide semiconductor supply chain we should at least get the numbers right.
