FinFET vs FDSOI – Which is the Right One for Your Design?

As a professional conference goer I can see definite trends when it comes to topics and attendance. Thus far this year I have seen a double digit increase in attendance, which is great. The question is why? Why is the fabless semiconductor ecosystem leaving the safety of their cubicles and computer screens in droves to mingle amongst the masses? The answer I believe is that modern semiconductor design is moving faster than ever before and people are scrambling to keep up, absolutely.

When it comes to choosing a topic and organizing a session I have the advantage of SemiWiki analytics. I see what thousands of semiconductor people search for, read, and share, which is why the first session I did for EDPS was an introduction to FinFETs in 2013. Last year it was all about IP Integration issues and this year it is the design issues between FD-SOI and FinFET. Tom Dillinger of Oracle will keynote, below is the abstract and session summary. After the keynote there will be a panel discussion with Tom, Kelvin Low of Samsung Foundry, Boris Murmann of Stanford University, Jamie Schaeffer of GlobalFoundries, and Marco Brambilla of Synapse.

EDPS is more of a workshop than a regular conference. The advantage is that a workshop is smaller and more interactive. Not only do you get to see experts speak and interact with the audience, you get to have breakfast, lunch and dinner with them as well.

FinFET vs FDSOI – Which is the Right One for Your Design?
The emergence of multiple transistor technology options at today’s deep submicron process nodes introduces a variety of power, performance, and area tradeoffs. This session will start with an overview of the FinFET and Fully-Depleted Silicon-on-Insulator devices (FD-SOI, also known as Ultra-Thin Body SOI), in comparison to traditional bulk planar transistor technology. The session will then delve into a detailed discussion of the architectural and circuit implementation tradeoffs of these new offerings, to assist designers make the right choice for their target application.

This session will delve into the design tradeoffs associated with leading semiconductor manufacturing nodes, covering advanced bulk planar, Fully-Depleted SOI, and FinFET device options.

The kickoff presentation will establish a technical foundation for these processes, followed by a discussion of hands-on experiences from experts who are leading advanced chip designs and process implementations in these technologies. After the kickoff and brief presentations from the expert panel, attendees are encouraged to participate in a question-and-answer session, to explore specific process selection and implementation tradeoff decisions.

The kickoff will start with an introduction to bulk planar, FD-SOI, and FinFET devices – i.e., device cross-sections (and the associated parasitic elements); device fabrication options; and, sources of device variation. The compact models for these device types useful for circuit design and simulation will be reviewed. Advanced process technologies introduce additional device and circuit layout considerations – e.g., layout dependent effects, layout parasitic extraction (and parasitic reduction) around the device, and the importance and impact of lithographic uniformity in circuit layouts.

The kickoff will then move to circuit-level design considerations for library logic cells, for these different process options. Analog cells also have a key impact upon technology choice, and will be discussed as well (albeit briefly).

Finally, the kickoff will cover broader design methodology tradeoffs for these process options, specifically methods for making path-level and block-level power/performance optimizations. The design implementation methods for power, performance, and area (PPA) closure are key differentiating features of these technologies.

With this background, the expert panel will discuss some of their recent design and development experiences – choosing the optimum technology, making global and local implementation choices to meet PPA goals, and accommodating process technology variation in design closure.