A tower-like heterogeneous packaging architecture for the AI era VEMC: The Vertical System…Read More
Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI SiliconThe momentum behind RISC-V continues to accelerate as…Read More
Agentic AI and the Future of Chip Design: From Productivity Tool to Engineering PartnerHighlights from a recent panel session moderated by…Read More
How llmda.ai Coaxed Me Out of Retirement, an Interview with Kurt ShulerArteris is one of the most impressive companies…Read More
The Memory Sector Is Becoming One of the Main Beneficiaries of the AI BoomThe explosive growth of artificial intelligence is transforming…Read More
Brian Bailey at EETimes has an interesting interview with Kathryn Kranen. He says that the interview will be published in installments but the first one is up here. This first installment is mostly about how long-lived EDA companies (and others) have become since it takes a long time to build up enough revenue to be able to IPO.
She… Read More
Mentor has a webinar on Model Driven Development (MDD) for Systems Engineering, presented by Bill Chown. It is actually the first of 15 webinars. This first one is just over 30 minutes long and I assume the others will be too. The webinar focuses on embedded system development, which historically has largely been validated using… Read More
In the last few decades, electronics has become more and more central to our lives. When I was a child the only electronics in the house was the radio and the television, both of which contained tubes. Two big things happened that upended that world: the invention of the transistor and the invention of the integrated circuit. A modern… Read More
Why making the difference between chips and cores, when mentioning that CEVA’s customers have shipped four billion IC to date? Because that can make a big difference! Imagine for example an IP vendor selling processor IP cores to be used in massively parallel computing application, when the chip maker create a processor NxM matrix,… Read More
The Silicon Valley CDNLive, the Cadence user conference, will be on March 12-13th 2013 in Santa Clara. But the heart of CDNLive are customer presentations and the call for papers is now open. The deadline is December 4th (at 5pm PST for people who really like to come down to the wire). At this point only an abstract is required.
There… Read More
The 2nd International Workshop on Resistive RAM. The workshop was the second installment of an annual series organized by Stanford University and the Belgian research institute Imec. Like most RRAM workshops, this year’s event featured talks focusing on the physics of RRAM devices and their underlying switching mechanism(s).… Read More
This year’s Renesas DevCon in Orange County, CA kicked off yesterday with an impressive lineup of speakers, record attendance, and an increased focus on automotive.
“TheAuto Industry Speaks,” an Expert Panel organized by Martin Bakerof Renesas, featured:
Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.
The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More
In April I attended and blogged about a webinar on MEMS and IC co-design hosted by two EDA companies: SoftMEMS and Tanner EDA. On October 30th you can attend a full-day event in Israel that is more comprehensive than the webinar that I attended.… Read More
In my blog about Intel’s latest results I linked to an interesting article in Wired about Google’s datacenters.
I happened to be browsing some websites in the Netherlands (actually I don’t speak a word of Dutch, a Dutch friend pointed it out to me) and there is an article showing how the pictures that accompany… Read More
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