Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative MattersThe future of work will not be shaped…Read More
Foundation IP for Intel 18A: Technical Overview and Why It MattersSynopsys Foundation IP for Intel 18A is a…Read More
WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA toolsThe real promise of AI in EDA is…Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too LateChip-level vulnerability is becoming an existential threat for…Read More
Why Real-Time Intelligence is the Next Differentiator in Semiconductor TestEven with advances in AI, automation, and advanced…Read More
I talked to Michael Buehler-Garcia about the changes Mentor is making to U2U, their user conference. It is in San Jose on April 25th at the DoubleTree.
Firstly, there are 3 great keynotes, two of whom I’ve seen speak before and can unreservedly recommend. Unfortunately I’m traveling that week and won’t be able… Read More
Cadence has brought a suit against Berkeley Design Automation for, as far as I can see, integrating their AFS circuit simulator with the Virtuoso Analog Design Environment (ADE) without using the (licensed) Oasis product. Since BDA is (actually was) a member of the Cadence Connections program, they have to abide by the contract… Read More
I hosted a webinar today for GlobalFoundries. Yes, I know that today was TSMC’s Technology Symposium, we weren’t that smart when we picked the date. It was basically a “fireside chat” with me as the moderator asking the questions and Paul Colestock and Aabid Husain as my guests. We actually did it at Cadence… Read More
As we have moved towards lower process nodes to improve performance of ICs with higher density and functionality, many manufacturing effects have appeared which can render ICs useless, even though the layout design could be correct as per traditional design rules. What is more worrisome is the variability of these effects which… Read More
TSMC has a lot of capacity. Not just that, it has a lot more under construction. It currently has 3 300mm Gigafabs, fabs 12,14 and 15 (there doesn’t seem to be a 13). This morning, Dr Wang, who is TSMC’s VP of 300mm operations told us about the expansion plans. Currently fab 15 phase 3 and 4, and fab 12 phase 3 are to be ramped… Read More
More so than most aspects of design, power reduction suffers from a paradox that early in the design cycle when the gains are the largest, the accuracy of power estimation is the lowest, and then late in the design cycle, when everything is known pretty much exactly it is too late to make anything other than trivial optimizations. … Read More
At DAC in 2012 I visited a few dozen EDA companies and blogged 32 articles, however I didn’t get to see what Apache Design (now a subsidiary of ANSYS) had to say. I did have 20 minutes today to watch their latest video on SoC Power Integrity Challenges and decided to share what I learned. If you want to watch the video at Tech Online,… Read More
One of the nice things about being part of a website such as SemiWiki is that you get to see real-time trends and analytics. SemiWiki is built on top of a relational database with a full content manager and integrated analytics. It also allows us to see historical data that we can compare and contrast to what is happening today.
One of… Read More
It appears that immersion lithography is now the plan of record for manufacturing ICs at 14nm. How is it possible to use 193nm wavelength light at 14nm? How can we provide the process window to pattern the such tight pitches? The secret lies in computational lithography. For 20nm, the two key innovations in computational lithography… Read More
… is now 8 years old, and the money paid for this 10 engineers start-up was considered, at that time, as a “bingo” for Cascade’s funders: “In October 2004, the Company completed the acquisition of Cascade Semiconductor Solutions, Inc. (Cascade) for total upfront consideration of $15.8 million and contingent consideration of … Read More
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The Packaging PDK Is the Missing Layer for Co-Packaged Optics