Accelerating Simulation. Innovation in VerificationFollowing a similar topic we covered early last…Read More
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Consumer memory slowing more than AI gainingConsumer memory slowing more than AI gaining causing…Read More
Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More
3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More
If you are not familiar with SuperSpeed USB standard (USB 3.0), you may understand this press release from Rahman Ismail, chief technology officer of the USB Implementers Forum, as simply claiming that USB 3.0 will be used in smartphone & media tablet this year… but, if you are familiar with the new standard, you are just confused!… Read More
DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More
“Before we acquire great power we must acquire wisdom to use it well”
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Making good architectural decisions for controlling power consumption and ensuring power integrity requires a good analysis of the current requirements and how they vary. Low power designs, and today there really aren’t… Read More
I’ve read about MoSys over the years and had the chance this week to interview Nani Subraminian, Engineering Manager about the types of EDA tools that they use and how design data management has been deployed to keep the design process organized. My background includes both DRAM and SRAM design, so I’ve been curious… Read More
Since the introduction of Apple’s iPhone and then the follow on iPAD, it has been Wall Streets frame of reference that Intel would be playing defense as the PC market slid into oblivion and therefore a Terminal Value should be placed on the company. Intel’s Q4 2011 earnings conference call provided a nice jolt to the analysts as Paul… Read More
Humor can arise in surprising ways and yet still be disguised to many. As I was researching Qualcomm the other day, I came upon the transcript of their last quarterly earnings and I had to laugh. In the midst of last summer’s European crises, when the Club Med (Greece, Italy, Spain and Portugal) Sovereign Debt was trying to be rolled… Read More
Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:
But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More
The need for Network-on-Chip (NoC) has appeared at the time where chip makers realized that they could really integrate a complete system on a single die to build a System-on-Chip (SoC). I was in charge of the development of a large IC, integrating different type of functions (Analog and Digital) to support advanced TV application.… Read More
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CES 2025 and all things Cycling