Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon SecurityIn a significant advancement for the semiconductor industry,…Read More
Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic EngineeringAt the 2026 Chiplet Summit, Synopsys presented a…Read More
An Agentic Formal Verifier. Innovation in VerificationIn a break from our academic-centric picks, here…Read More
Reimagining Compute in the Age of Dispersed IntelligenceAt the 2025 RISC-V Summit, amid debates over…Read More
Siemens to Deliver Industry-Leading PCB Test Engineering SolutionsSiemens has strengthened its position in EDA and…Read More
This year’s Mentor Graphics user group meeting, User2User, will be held at the DoubleTree by Hilton in San Jose, California on April 25, 2013. The featured keynote presenters include…
The cell phone phenomena has catalyzed the technology growth and coaxed the hardware and software to work more closely. The Apple effect further directed this technology growth to focus on enhanced user experience. The emphasis has been primarily on the display and touch aspects of the designs with limited adoption on other areas.… Read More
Worldwide electronics bounced back strongly in 2010 after the recession of 2008-2009. Every region experienced solid growth, ranging from high single-digit growth in the U.S. to over 20% in the key Asian countries. However in the last two years electronics has slowed down significantly. Several factors contributed to this … Read More
I talked to Dado Banatao today. He is managing partner at Tallwood Venture Capital today but back in the mid-1980s he was the founder of Chips and Technologies, the first fabless semiconductor company. The rumors that they had a hard time raising money because VCs couldn’t comprehend a fabless semiconductor company are … Read More
I was at the EDAC CEO forecast meeting last week and one of the questions that was asked of EDAC members was “which is the hottest EDA startup?” The one with the most nominations was Oasys. So Oasys is hot.
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The latest announcement from Oasys this morning is that register retiming is now … Read More
Mixed-Signal design is one of the very initial design methodologies, pioneered by Cadence with its lead in custom design; now taking centre space in the world of SoCs. Its growth is surmountable as it finds its place in most of the high growth electronics like smart phones, automotive applications, networks and communications,… Read More
So Ericsson Mobile Platforms is to be shut down, with the loss of around 1600 jobs. Not to mention billions of dollars that ST and Ericsson sunk into the joint venture in an attempt to create a competitor to Qualcomm.
The history actually goes back a bit further. Nokia originally had an internal semiconductor design group and in 2007… Read More
The Network On Chip (NoC) concept is recent, about 10 years old, and the first implementation of commercially available NoC IP has happened in 2006. Should we drop the concept so quickly after it has been introduced? In fact, I don’t think so… But we could brain storm and imagine the new functions that could be implemented within or… Read More
A dedicated schematic migration tool can save weeks of effort and allow companies to explore new foundry opportunities. Unfortunately moving analog and mixed signal design data between foundries and processes is a complex business. While engineers would rather spend their days creating new circuits, many spend time translating… Read More
The challenges of developing IP blocks, integrating them correctly, and hitting the power, performance, area, and time to market requirements of a mobile SoC is a growing problem. At 20nm and 14nm the probability of a chip re-spin due to an error is approaching 50% and we all know how disastrous a re-spin can be, those are not good … Read More
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Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability