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IC design at 20nm with TSMC and Synopsys

IC design at 20nm with TSMC and Synopsys
by Daniel Payne on 05-02-2012 at 10:25 am

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While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More


ARM Models: Carbon Inside

ARM Models: Carbon Inside
by Paul McLellan on 05-01-2012 at 10:00 pm

ARM used to build their own models. By hand. They had an instruction-set simulator (ISS) called ARMulator that was largely intended for software development, and cycle-accurate models that were intended to run within digital simulators for development of the hardware of ARM-based systems.

There were two problems with this … Read More


RedHawk: On to the Future

RedHawk: On to the Future
by Paul McLellan on 05-01-2012 at 6:00 am

For many, maybe most, big designs, Apache’s RedHawk is the signoff tool for analyzing issues around power: electromigration, power supply droop, noise, transients and so on. But the latest designs have some issues: they are enormous (so you can’t just analyze them naively any more than you can run a Spice simulation… Read More


Book Review – Quantum Physics: A Beginner’s Guide

Book Review – Quantum Physics: A Beginner’s Guide
by Daniel Payne on 04-30-2012 at 8:00 am

It’s been 34 years since I graduated from the University of Minnesota with a degree in Electrical Engineering so I was curious about what has changed in quantum physics since then. Alastair Rae is the UK-based author who wrote the book – Quantum Physics: A Beginner’s Guide. I read this on my Kindle Touch e-book… Read More


Such a small piece of Silicon, so strategic PHY IP

Such a small piece of Silicon, so strategic PHY IP
by Eric Esteve on 04-30-2012 at 6:05 am

How could I talk about the various Interface protocols (PCIe, USB, MIPI, DDRn…) from an IP perspective and miss the PHY IP! Especially these days, where the PHY IP market has been seriously shaken, as we will see in this post, and will probably continue to be shaken… but we will have to wait and look at the M&A news during the next … Read More


GSA 3DIC and Cadence

GSA 3DIC and Cadence
by Paul McLellan on 04-29-2012 at 10:00 pm

At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position… Read More


Smart mobile SoCs: Apple

Smart mobile SoCs: Apple
by Don Dingee on 04-29-2012 at 9:00 pm

Apple sells devices. Lots of them. Their success is due to many things related to design and tech religion, and an important part is the SoC inside those devices which creates the experience people want. The official Apple information on their parts is minimal. Their SoCs have been dissected with more fervor than Roswell aliens.… Read More


A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design

A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design
by Eric Filseth on 04-29-2012 at 9:00 pm

At 28nm and below, a number of electrical variation effects become significant which depend not only on individual devices, but the physical interaction between neighboring devices, wells, etc during the manufacturing process. Some of these effects have become collectively referred to as “Layout Dependent Effects” (LDE);… Read More


Intel says fabless model collapsing… really?

Intel says fabless model collapsing… really?
by Daniel Nenni on 04-28-2012 at 7:00 pm

There is an interesting discussion in the SemiWiki forum in response to the EETimes article: Intel exec says fabless model ‘collapsing’. Definitely an interesting debate, one worth our time since the advertising click hungry industry pundits will certainly jump all over it. Clearly I’m biased since I helped build… Read More


IC Reliability and Prevention During Design with EDA Tools

IC Reliability and Prevention During Design with EDA Tools
by Daniel Payne on 04-27-2012 at 5:04 pm

IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More