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Cadence’s NVM Express: fruit from subsystem IP based strategy

Cadence’s NVM Express: fruit from subsystem IP based strategy
by Eric Esteve on 07-02-2012 at 11:24 am

If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More


Crushed Blackberry

Crushed Blackberry
by Paul McLellan on 07-02-2012 at 12:00 am

I wasn’t going to write about the cell phone business again for some time. After all, this is a site about semiconductor and EDA primarily. But the cell-phone business in all its facets is a huge semiconductor consumer and continues to grow fast (despite my morbid focus on those companies that do anything but).

But Research… Read More


Synopsys IP Strategy 2012

Synopsys IP Strategy 2012
by Daniel Nenni on 07-01-2012 at 7:30 pm

Synopsys is the dominant player in the commercial EDA and semiconductor IP markets so it is always interesting to hear what John Koeter, Vice President of Marketing for IP, Services and System Level Solutions, has to say. John presented “The Role of IP in a Changing Landscape” at the SemiCO IMPACT Conference and I talked to him again… Read More


Dragon Boats and TSMC 20nm Update!

Dragon Boats and TSMC 20nm Update!
by Daniel Nenni on 07-01-2012 at 6:30 pm


My luck continues as I missed last week’s typhoon. Fortunately it did not disrupt the annual Dragon Boat Festival. More than just a Chinese tradition, dragon boat racing is an international sports event with teams from around the world coming to Taiwan every year. It is very exciting with the colorful dragon boats and the wild beating… Read More


The Scariest Graph I’ve Seen Recently

The Scariest Graph I’ve Seen Recently
by Paul McLellan on 07-01-2012 at 4:00 pm

Everyone knows Moore’s Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives… Read More


Chip Synthesis at DAC

Chip Synthesis at DAC
by Paul McLellan on 06-27-2012 at 8:30 pm

I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have… Read More


TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work … Read More


Robustness, Reliability and Yield at DAC

Robustness, Reliability and Yield at DAC
by Daniel Payne on 06-26-2012 at 8:15 pm

On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:

  • Schematic porting
  • Nominal circuit analysis
  • Nominal circuit optimization
  • Statistical circuit analysis
  • Statistical circuit optimization
  • IP porting
  • Circuit model generation
Read More