Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
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The Sondrel transformation to Aion SIlicon!Ollie is a commercially astute senior leader with…Read More
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We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.
Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce.… Read More
Scott Seaton is the new CEO of Oasys Design Systems. Paul van Besouw, the CEO since the company’s founding, becomes the CTO. I met Scott last year when I was doing some consulting work for Carbon Design where he was VP of sales (the new VP sales at Carbon is Hal Conklin, by the way).
I talked to Scott about why he had joined Oasys. … Read More
We all know the concept of “one stop shop”, becoming popular in the Design IP market. The topic we will address today is NOT the “one stop shop”, even if it looks similar, but rather that we could call “consistent design flow”.
What does that means? Simply that, if your SoC design is integrating a DDRn (LPDDR2, DDR3 or even DDR4, let’s… Read More
David Avercrombie of Mentor won the award for the best tutorial at the 2012 TSMC OIP for his presentation, along with Peter Hsu of TSMC, on Finding and Fixing Double Patterning Errors in 20nm. The whole presentation along with the slides is now available online here. The first part of the presentation is an introduction to double … Read More
At TSMC’s Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described below with links to downloadable pdf presentation files.
Finding and Fixing Double Patterning Errors in… Read More
Apache Design Solutions was founded in 2001 by Andrew Yang and three researchers from HP Labs (Norman Chang, Shen Lin, Weize Xie). They realized that engineers striving to meet the goal of increased device miniaturization, as defined by Moore’s Law, would eventually hit stumbling blocks in their progress. The founding team believed… Read More
A quick re-introduction of ReRAM-Forum.com which is dedicated to all things related to resistive RAM, broadly characterized as ReRAM (or RRAM) and CBRAM. The technology is seen as the ‘next generation’ non-volatile memory solution and is being developed by companies large and small for a variety of applications in storage, … Read More
Like any other event, the Consumer Electronics Show in Las Vegas is not immune to unethical and inappropriate behavior. Unfortunately one of digital media’s finest got caught this year doing what most publications have done since the beginning of time. CNET bowed to pressure from above and changed the outcome of the annual… Read More
I’ve taught Verilog classes and used logic synthesis tools for ASIC and FPGA designs, so was interested to hear about Oasys Design Systems. I attended their webinar at 9AM today, so I’ll share what I learned about their approach to logical and physical synthesis. This approach competes with tools like Design Compiler… Read More
SuperSpeed USB has been clearly ranked in the Interface protocols winner list, see this previous post. It could be interesting to dig into this IP market segment, determine in which applications USB 3.0 has been successfully deployed and who are the IP vendors serving this market, enabling SuperSpeed USB to take off.
SuperSpeed… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot