When Software Outruns Silicon: Hardware-Assisted Test Generation to the RescueFor the past decade, the semiconductor industry has…Read More
From Tokens to Infrastructure: Why Compute, Memory, and Power Will Determine the Future of AIBased on Dylan Patel’s SEMI Industry Strategy Symposium…Read More
Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?Intel’s 18A process technology has become one of…Read More
WEBINAR: Why Google Cloud NetApp Volumes Matter for Modern EDA WorkloadsIn this webinar, Google Cloud and NetApp explore…Read More
How to Free Yourself from Inconsistent Engineering Documentation Before It’s Too LateEmbedded systems programs often fail because critical engineering…Read More
The smartphone is becoming a commodity, a lifecycle stage where the strong get stronger, the weak get weaker, and the products standardize and start to look alike. This dynamic is driving innovation in existing products to extremes and spawning a new class of wearable devices.
Today two major players are leading the mobile hardware… Read More
This week Xilinx has announced that “The Xilinx 20nm All Programmable UltraScale™ portfolio is now available with detailed device tables, product documentation, design tools and methodology support.”
Do you know what 20nm is? It’s small, tiny. Think about it this way, as I just learned today that one nanometer is about as long… Read More
Jim Feldhan, President of Semico Research presented earlier this month at the Impact Conference on the topic: Focus on the IP Ecosystem. I’ve reviewed his 19 page presentation, and summarize it with:
Donald Rumsfeld categorized what we knew into known unknowns and unknown unknowns. In a chip design, those unknown unknowns can bite you and leave you with a non-functional design, perhaps even intermittent failures which can be among the hardest problems to debug.
Chips are too big to do any sort of full gate-level simulation,… Read More
My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More
As a full time financial writer/investor, I am always on the lookout for compelling risk/reward opportunities, particularly in small-cap tech. While the world of large-cap tech is generally well understood by the investment/analyst community, smaller cap names are usually under-followed and often misunderstood. One such… Read More
Next year’s DVCon attendees can expect to learn about both practical solutions to their pressing problems that can be applied today and also receive a preview of the technologies that will affect them in the near future. DVCON is March 3-6, 2014 @ the DoubleTree Hotel in San Jose.
KEYNOTE: An Executive View of Trends and Technologies… Read More
We agree now that FD-SOI technology is Faster, Cooler, Simpler. But can it also be a cheaper technology? Let start with an overview of the current estimation of the development cost for complex SoC on advanced technology nodes. The following data are extracted from International Business Strategies, Inc 2013 report. The first… Read More
SEMI’s World Fab Forecast report, published in November, predicts that fab equipment spending will decline about -9 percent (US$32.5 billion) in 2013 (including new, used and in-house manufactured equipment). Setting aside the used 300mm equipment Globalfoundries acquired from Promos at the beginning of 2013 (NT$20-30 … Read More
Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More
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