Broadcom Told the Truth. The Market Hasn’t Heard the Rest of It Yet.Hock Tan and his CFO Kirsten Spears logged…Read More
CEO Interview with Chuck Gershman of Owl Autonomous ImagingChuck Gershman is the CEO and co-founder of…Read More
CEO Interview with Daniel Schall of Black SemiconductorDr. Daniel Schall is CEO and Co-Founder of…Read More
Alchip Accelerates on AI ASIC DemandAlchip Technologies reported improved financial results for the…Read More
Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys ToolsAs advanced packaging becomes a critical enabler for…Read More
In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent… Read More
In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle… Read More
Cadence announced today that it is acquiring Jasper Design Automation for $170M in an all-cash offer. Jasper has $24M in cash so it is really an acquisition for around $145M. i think that is around 4X revenue but I only know rumors about Jasper’s revenue numbers.
All the big 3 already have their own formal technology but the … Read More
Pop quiz: Name one of the hottest applications for non-volatile memory – A) processor and code configuration; B) RFID tags; C) secure encryption keys; D) all the above. The answer is D, but not in the way you may be thinking; a new approach is using all these ideas at once, combined in SoC designs targeting advanced security … Read More
I went to a briefing last Tuesday where Samsung and GlobalFoundries announced that they have the same process at 14nm. Dan already wrote about itso it is old news in one sense. But I really think people underestimate its importance. In essence, reading between the lines, Samsung is licensing GF their 14nm process. This is driven … Read More
At DVCon Lawrence Loh and Viktor Markus Purri gave a tutorial on Formally Verifying Security Aspects of SoC Designs. Lawrence is the direector of WW application engineering and Markus is an FAE who specializes in security verification.
I’m not going to attempt to summarize an entire half-day tutorial in under 1000 words,… Read More
A few years ago my then-girlfriend was an artist and she had some friends who were in the maker movement, one who ran a tool “lending library” and so on. So she wanted to go to the Maker Faire, which is a huge event held in San Mateo exhibit center. In those days it was more like an outgrowth of burning man but there were already… Read More
This was one of the most memorable keynotes I have seen, absolutely. Probably because it supports my belief that the infamous Intel slide that “projected” Intel will continue a linear manufacturing cost per transistor improvement at 14nm and 10nm is pure marketing fluff. Even more interesting, according to Intel, other semiconductor… Read More
There are always a number of other events that are colocated with DAC. One this year is the 23rd International Workshop on Logic and Synthesis (IWLS) that is held the weekend before DAC on May 30th and June 1st. Strictly speaking it is not colocated since it is in the Galleria Park Hotel on Sutter Street a few blocks away whereas DAC itself… Read More
I was at EDPS in Monterey the last couple of days. It is one of the most interesting conferences to attend. Go next year since you already missed it this year. It is not big but the quality of the content is high. Historically the dinner in the middle is in the Monterey Yacht Club and there is a keynote speech. A few years ago it was me but this… Read More
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