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Increase Your Chip Reliability with iROC Tech

Increase Your Chip Reliability with iROC Tech
by Pawan Fangaria on 06-12-2013 at 9:00 pm

As we have moved towards extremely low process nodes with very high chip density, the cost of mask preparation also has become exorbitantly high. It has become essential to know about the failure rates and mitigate the same at the design time before chip fabrication, and also to make sure about chip reliability over time as it is constantly… Read More


So, where are all the EMBEDDED guys?

So, where are all the EMBEDDED guys?
by Don Dingee on 06-12-2013 at 8:15 pm

Roaming the aisles at #50DAC the past week left me with one unmistakable impression: there were two shows going on at the same time. Oh, we were all packed into one space together at the Austin Convention Center and neighboring hotels. But we weren’t quite all speaking the same language – yet.… Read More


A Call to ARMs!

A Call to ARMs!
by Daniel Nenni on 06-12-2013 at 7:00 pm

It sure has been an interesting experience watching Intel enter the semiconductor foundry business! While I credit Intel for increasing the exposure of the fabless semiconductor ecosystem to the financial markets, the attention from the Intel biased press is a bit overwhelming. The TSMC and ARM bashing is reaching new levels… Read More


Hardware Assisted Verification

Hardware Assisted Verification
by Paul McLellan on 06-10-2013 at 9:00 pm

On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More


Custom Physical IC Design update from Cadence

Custom Physical IC Design update from Cadence
by Daniel Payne on 06-10-2013 at 8:05 pm

Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.


John StabenowRead More


ARM Update at DAC

ARM Update at DAC
by Daniel Payne on 06-10-2013 at 7:09 pm

John Heinleinfrom ARM briefed me at DAC exactly one week ago. I love to use my mobile devices (MacBook Pro, iPad and Samsung Galaxy Note II) every day, and many mobile devices are ARM-powered because of the low power consumption, and pervasive eco-system around the architecture. Apple with the MacBook Pro is still Intel-powered,… Read More


AMS IC Simulation Update from Synopsys at DAC

AMS IC Simulation Update from Synopsys at DAC
by Daniel Payne on 06-10-2013 at 6:19 pm

Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:

  • HSPICE continues on, although it’s a lower performance circuit simulator than FineSim
  • FineSim from Magma is well-loved, and faster than HSPICE
Read More

Using Releases for Analog IC Design

Using Releases for Analog IC Design
by Daniel Payne on 06-10-2013 at 1:11 pm

In a typical analog IC design team, multiple engineers and layout professionals work on cells and libraries. At various points during the design process they will commit changes to their designs into the Design Management (DM) system that manages their files – be it Subversion, Perforce or some other commercial tool.

Using the… Read More


Meeting with Sidense at TSMC Technology Symposium

Meeting with Sidense at TSMC Technology Symposium
by Eric Esteve on 06-10-2013 at 11:34 am

If you have attended DAC in Austin (June 2-5), you probably have missed the first TSMC Technology Symposium. It was held on June 6 in Shanghai. Considering my own experience of a 29 hours trip to come back home (in France), I doubt that it was any possible to leave Austin on June 5 to attend TSMC Technology Symposium in Shanghai on June… Read More


GSA Entrepreneurship Conference

GSA Entrepreneurship Conference
by Paul McLellan on 06-10-2013 at 12:04 am

GSA’s next event is the annual Entrepreneurship Conference to be held at the Computer History Museum on July 18th. The event runs from 3pm to 8pm. Attendance is free but you must register here.

The event consists of 5 panel sessions followed by a reception. The full roster of who will be on each panel is not completely finalized… Read More