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Mixed Signal SOC verification Webinar

Mixed Signal SOC verification Webinar
by Daniel Payne on 07-16-2013 at 8:29 pm

When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

A second trend is the amount of Analog content in… Read More


Novati Covers the Periodic Table

Novati Covers the Periodic Table
by Paul McLellan on 07-16-2013 at 4:59 pm

Novati is a semiconductor company that you probably haven’t heard of. It has its roots in Sematech back when Sematech was mainly in Austin rather than New York where it is today. The Sematech fab first became an independent company and then acquired by SVTC and operated under that name for 4 years. Finally, last the investors… Read More


VIA Adopts Cliosoft

VIA Adopts Cliosoft
by Paul McLellan on 07-16-2013 at 4:27 pm

VIA Telecom, who makes CDMA base-band processor chips, picked ClioSoft SOS for use by its analog mixed-signal design teams. Like many such teams they use Cadence’s Virtuoso layout platform. ClioSoft’s SOS is seamlessly integrated into Virtuoso so that designers don’t really need to spend much time worrying… Read More


Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs

Minimize the Cost of Testing ARM® Processor-based Designs and Other Multicore SoCs
by Daniel Payne on 07-15-2013 at 1:37 pm

On my first job out of college as an IC design engineer I was surprised to discover that a major cost of chips was in the amount of time spent on the tester before being shipped. That is still true today, so how would you keep your tester time down, test coverage high and with a minimum number of pins when using multiple processors on a single… Read More


Intel Benchmark Hoax!

Intel Benchmark Hoax!
by Daniel Nenni on 07-14-2013 at 7:00 pm

To be fair, cheating on CPU benchmarks is not new, so if you haven’t followed the computer industry for the past 30 years you might be surprised by Intel cheating, but I’m certainly not. Back in the day I worked for Data General and we “creatively” benchmarked against the Digital Equipment VAX all day long. There are different types… Read More


How to reduce routing congestion in large Application Processor SoC?

How to reduce routing congestion in large Application Processor SoC?
by Eric Esteve on 07-14-2013 at 10:22 am

Application Processor SoC integrates more and more functions, generation after generation, challenging performance, cost, power efficiency, reliability, and time-to-market. But the maximum die size can’t increase, at least because of the constraints linked with wafer production, manufacturability, yield and finally… Read More


Interview with Arasan

Interview with Arasan
by Daniel Nenni on 07-12-2013 at 7:00 pm


Recently I had a chance to chat with Arasan Ganesan, CEO at Arasan Chip Systems in San Jose, CA. Arasan Chip Systems has provided Silicon interface IP and supporting hardware and software to the semiconductor industry for more than 15 years. The headquarters are in San Jose and engineering offices in Bangalore and Tuticorin, India.… Read More


Testing an IC Sandwich

Testing an IC Sandwich
by Beth Martin on 07-12-2013 at 3:10 pm

At a lovely, but chilly, 3DIncites awards breakfast during SEMICON West, I saw Mentor Graphics win in two of five categories (Calibre 3DSTACK was the other winner). Afterwards, I talked to Steve Pateras, the product marketing director of Mentor’s test solutions about Tessent Memory BIST, which was one of the winners. I asked Pateras… Read More


Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform

Aldec Verifies Compatibility of Northwest Logic’s PCI Express Cores with HES-7™ SoC/ASIC Prototyping Platform
by Daniel Nenni on 07-12-2013 at 12:50 am

Henderson, Nevada – July 11, 2013 –Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, today announced that engineers incorporating high-speed PCI Express data transmission into their SoC and ASIC designs can accelerate their time-to-market utilizing Northwest LogicRead More


Data Centers accounts for 2 to 3% of WW Energy Consumption!

Data Centers accounts for 2 to 3% of WW Energy Consumption!
by Eric Esteve on 07-11-2013 at 8:19 am

Do you think this figure will go down? Considering the massive move to Mobile equipment, pushing to de-localize your storage medium to instead use the cloud capabilities, and looking at the huge number of people buying smartphone and tablet in emerging countries, no doubt that Data Center related energy consumption is expected… Read More