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Podcast EP290: Navigating the Shift to Quantum Safe Security with PQShield’s Graeme Hickey

Podcast EP290: Navigating the Shift to Quantum Safe Security with PQShield’s Graeme Hickey
by Daniel Nenni on 06-06-2025 at 6:00 am
Categories: PQShield, Security

Dan is joined by Graeme Hickey, vice president of engineering at PQShield. Graeme has over 25 years of experience in the semiconductor industry creating cryptographic IP and security subsystems for secure products. Formerly of NXP Semiconductor, he was senior manager of the company’s Secure Hardware Subsystems group responsible… Read More

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ChipAgent AI at the 2025 Design Automation Conference #62DAC

ChipAgent AI at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-05-2025 at 10:00 am
Categories: ChipAgents AI, EDA, Events

ChipAgentsAtDAC

The semiconductor world is gathering at DAC 62, and ChipAgents AI is coming ready to show why agentic AI is the missing piece in modern RTL design and verification. Whether you’re drowning in terabytes of waveform data, grinding toward 100% functional coverage, or hunting for ways to accelerate time-to-market, our sessions and… Read More

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proteanTecs at the 2025 Design Automation Conference #62DAC

proteanTecs at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-05-2025 at 8:00 am
Categories: Analytics, Events, proteanTecs

62nd DAC SemiWiki

Discover how proteanTecs is transforming health and performance monitoring across the semiconductor lifecycle to meet the growing demands of AI and Next-Gen SoCs.

Stop by DAC booth #1616 to experience our latest technologies in action, including interactive live demos and explore our full suite of solutions — designed to boost… Read More

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Arm Reveals Zena Automotive Compute Subsystem

Arm Reveals Zena Automotive Compute Subsystem
by Bernard Murphy on 06-05-2025 at 6:00 am
Categories: AI, Arm, Automotive, IP

Zena CSS min

Last year Arm announced their support for standards-based virtual prototyping in automotive, along with a portfolio of new AE (automotive enhanced) cores. They also suggested that in 2025 they would be following Arm directions in other LOBs by offering integrated compute subsystems (CSS). Now they have delivered: their Zena… Read More

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High-NA Hard Sell: EUV Multi-patterning Practices Revealed, Depth of Focus Not Mentioned

High-NA Hard Sell: EUV Multi-patterning Practices Revealed, Depth of Focus Not Mentioned
by Fred Chen on 06-04-2025 at 10:00 am
Categories: Lithography

HNA EUV Fred Chen

In High-NA EUV lithography systems, the numerical aperture (NA) is expanded from 0.33 to 0.55. This change has been marketed as allowing multi-patterning on the 0.33 NA EUV systems to be avoided. Only very recently have specific examples of this been provided [1]. In fact, it can be shown that double patterning has been implemented… Read More

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Anirudh Fireside Chats with Jensen and Lip-Bu at CadenceLIVE 2025

Anirudh Fireside Chats with Jensen and Lip-Bu at CadenceLIVE 2025
by Bernard Murphy on 06-04-2025 at 6:00 am
Categories: AI, Cadence, EDA, Intel Foundry

Anirudh with Jensen and Lip Bu

Anirudh (Cadence President and CEO) had two fireside chats during CadenceLIVE 2025, the first with Jensen Huang (Founder and CEO of NVIDIA) to kick off the show, and later in the day with Lip-Bu Tan (CEO of Intel). Of course Jensen and Lip-Bu also turn up for other big vendor shows but I was reminded that there is something special about… Read More

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TCAD for 3D Silicon Simulation

TCAD for 3D Silicon Simulation
by Daniel Payne on 06-03-2025 at 10:00 am
Categories: EDA, Silvaco

Silvaco TCAD min

Semiconductor fabs aim to have high yields and provide processes that attract design firms and win new design starts, but how does a fab deliver their process nodes in a timely manner without having to run lots of expensive silicon through the line? This is where simulation and TCAD tools come into play, and to learn more about this… Read More

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Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination

Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination
by Admin on 06-03-2025 at 6:00 am
Categories: IP, Weebit Nano
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Im1 Weebit Relaxation Aware Programming in ReRAM Optimizing Write Termination RRAM 1024x704

Resistive RAM (ReRAM or RRAM) is the strongest candidate for next-generation non-volatile memory (NVM), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called ‘relaxation’ are making ReRAM more predictable — and easier to specify for real-world applications.… Read More

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Breker Verification Systems at the 2025 Design Automation Conference #62DAC

Breker Verification Systems at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-02-2025 at 10:00 am
Categories: Breker Verification Systems, EDA, Events, RISC-V

62nd DAC SemiWiki

Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio

Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.… Read More

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The SemiWiki 62nd DAC Preview

The SemiWiki 62nd DAC Preview
by Daniel Nenni on 06-02-2025 at 6:00 am
Categories: AI, Chiplet, EDA, Events

62nd DAC SemiWiki

After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More