Every industry has famous thought leaders that can summarize where we’ve been and then paint a picture of where we’re headed towards in the future. Often they make statements that become industry expressions, like “Moore’s Law” or the “Internet of Things”. I think that if Synopsys… Read More




More knowledge, less time in FPGA-based prototyping
I recently published a post on LinkedIn titled “Sometimes, you gotta throw it all out” in reference to the innovation process and getting beyond good to better. A prime example has crossed my desk: the new ProtoCompiler software for Synopsys HAPS FPGA-based prototyping systems.
Last week, I spoke with Troy Scott, product marketing… Read More
Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance
Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More
Xilinx Quarterly Results: 20nm Prototypes
Xilinx announced their quarterly results last week. Because of their financial year not being aligned with their calendar year this is actually 4th quarter of their 2014 financial year. New Year’s Eve 2015 comes early for Xilinx. The results were very good. As Moshe Gavrielov, the CEO, said on the conference call:Xilinx… Read More
Carey Robertson: Reliability Checks in Advanced Nodes
Last week I had the pleasure of presenting at the Electronic Design Process Symposium (EDPS) workshop. This was my first time attending and I was very impressed. There were good presentations but I learned as much from the Q&A and the side conversations before/after/breakfast/lunch/etc. If you have the opportunity to attend,… Read More
FinFET & Multi-patterning Need Special P&R Handling
I think by now a lot has been said about the necessity of multi-patterning at advanced technology nodes with extremely low feature size such as 20nm, because lithography using 193nm wavelength of light makes printing and manufacturing of semiconductor design very difficult. The multi-patterning is a novel semiconductor manufacturing… Read More
Dr. Bernard Murphy: My presentation at EDPS 2014
First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3[SUP]rd[/SUP]-party IP qualification for the TSMC soft IP library.
My presentation slides are located here:
http://www.eda.org/edps/Papers/5-3%20Bernard%20Murphy.pdf… Read More
Calling all makers for new #8bitideas
The maker community and the learn-to-code movement is growing with many ideas built on small, power-efficient, easy-to-use 8-bit microcontrollers. If you want to be one of the next famous makers and maybe win some cash in the process, Atmel has a contest open until September 30, 2014 – here are tips on getting your #8bitideas in … Read More
FD-SOI Better Than FinFET?
As I said earlier in the month, I was going to be talking about FD-SOI at the Electronic Design Process Symposium (EDPS) in Monterey. I am not especially an expert on FD-SOI but I know enough to be dangerous and given that we were already talking about FinFET and 3D/2.5D chips, it fitted in nicely.
The 10,000 foot view is that FD-SOI has… Read More
TSMC Will Own the Internet of Things!
In my quest to uncover the future of the semiconductor industry I was quite impressed by the executive presentations at the TSMC Symposium last week. Rick Cassidy opened the 20[SUP]th[/SUP] Annual TSMC Technology Symposium followed by Dr. Mark Liu, Dr. Jack Sun, Dr. Cliff Hou, J.K Wang, Dr. V.J. Wu, and Suk Lee. A variety of topics… Read More
Should the US Government Invest in Intel?