Suresh is a technology executive with deep technical expertise in semiconductors, artificial intelligence, cybersecurity, internet-of-things, hardware, software, etc. He spent 20 years in the industry, most recently serving as an Executive Director for open-source zero-trust chip development at Technology Innovation… Read More
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Analysis and Verification of Single Event Upset Mitigation
The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power… Read More
5G Aim at LEO Satellites Will Stimulate Growth and Competition
Low earth orbit (LEO) satellites as an intermediary for communication became hot when Elon Musk announced Starlink (yeah, other options were available, but Elon Musk). This capability extends internet availability to remote areas and notably (for a while) to Ukraine in support of the war with Russia. Satellites can in principle… Read More
Do you have Time to Pull in your Tapeout Schedule?
So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.
You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise… Read More
Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
AI is here, there, and absolutely everywhere – now and forever.
The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:
- “AI Everywhere” delivered
BEOL Mask Reduction Using Spacer-Defined Vias and Cuts
In recent advanced nodes, via and cut patterning have constituted a larger and larger portion of the overall BEOL mask count. The advent of SALELE [1,2] caused mask count to increase for EUV as well, resulting in costs no longer being competitive with DUV down to 3nm [3]. Further development by TEL [4] has shown the possibility for… Read More
Prototyping Chiplets from the Desktop!
S2C has been successfully delivering rapid SoC prototyping solutions since 2003 with over 600 customers, including 6 of the world’s top 10 semiconductor companies. I personally have been involved with the prototyping market for a good part of my career and know S2C intimately.
S2C is the leading independent global supplier… Read More
Building Reliability into Advanced Automotive Electronics
Those of you who have been in the industry for a little while will remember that the recipe for reliable electronics in cars (and other vehicles) used to be simple. Stick to old (like 10 years old) and well-proven processes and tweak rather than tear up and restart well-proven designs to the greatest extent possible. Because incrementing… Read More
Improving Wafer Quality and Yield with UPW Resistivity and TOC Measurements
An earlier SemiWiki post discussed water sustainability in semiconductor manufacturing, related challenges and solutions. Whether first time use or recycled use, water purity needs to meet certain stringent criteria for the processing task on hand. This article will look at it from a wafer quality and yield perspective and… Read More
RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors… Read More
CHIPS Act dies because employees are fired – NIST CHIPS people are probationary