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[post_content] => Thanks to the Semiconductor Ecosystem Survey from GSA-Wharton and the key indicators of semiconductor companies’ technology strategies related to IP:
- IP Reuse: On average, a fabless semiconductor company reuses about 63% of design IP in the revision of an existing product design and about 44% in a new product design.
- Source of IP: Silicon foundries are becoming an important source of design IP for fabless companies in addition to third-party IP firms. On average, 18% of design IP blocks are from the foundry's portfolio/library, followed by 16% for third-party licensing firms.
The other key indicators are about differentiation and time-to-market.Let’s make some comments. First of all, as I am focusing on IP… I am happy, as the report clearly links IP as one of the major source of innovation. But, when I think to my blogger colleagues who’s focus is on EDA (namely, Dan Nenni, Daniel Payne and Paul McLellan), I think they have good reasons to be disappointed, as within the 26 pages you will never found the mention of EDA. The report is dealing about “Innovation”, “partners” and “ecosystem”, referring to the fables companies, so –intentionally or not- deciding to omit EDA companies in the ecosystem looks strange to me… Let’s come back to IP. The number of design IP blocks coming from foundries (18%) is higher than these coming from the IP vendors (16%). Is it a surprise? No, as when looking at the list of IP offered by the major foundries, you realize that this list is pretty long, even if we can qualify these IP as commodities in most of the cases. Yes if you consider the large number of IP vendors (more than 460 listed on D&R). They have to offer differentiated products to compete with their foundry partners! The other figure, 66% of design IP blocks are being internally sourced by the fabless, certainly opens a growth opportunity for the IP “providers” (foundry or IP vendor). We all know that the trend is, and will be, to outsource more design IP blocks, with a limit defined by the fabless themselves: you don’t want to outsource the part of the design on which you build your differentiation. We can guess that these differentiating functions represent a lot less than 66% of the design blocks. The real number is probably in the 20 to 30% range, say 25%, arbitrary. Now, the question is to know how long it will take for the fables to move from 66% down to 25% of internally reused IP blocks: 5 years? 10 years? 
Let’s look at these two scenarios and forecast the effect on the IP market size growth rate. In one case, the IP market would move from 16% (of design blocks) to 37% in 2015 (assuming the outsourcing is equally shared by the IP vendors and the foundries, which is certainly not right, but the “less wrong” assumption we can make here).
If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 18%, and a market size passing from $1 677M in 2010 to $3 850M in 2015.
But we know that many other effects can generate the growth: the emergence of new protocols is pushing the fabless or IDM to outsource the function, because it is too complex to design, or require competencies not available within the company. The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP. Or new functions issued from innovation, which simply did not exist before, and have to be licensed to the inventors (HDMI is a good example). This to say that the size of the market will be larger than that we have found by only using the growth of outsourcing rate! This 18% CAGR is impressive, especially when you consider the other growth factors for the IP market: · The emergence of new protocols, pushing the fabless or IDM to outsource the function, because it is too complex or too long to design, or require competencies not available within the company.· The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP.· Or to integrate new functions issued from innovation, which simply did not exist before, when the shortest path is to licensed it, to the inventors or IP vendors (HDMI is a good example).This to say that the market size should be larger than that we have found by only using the growth of outsourcing rate, so the assumption based on a 5 years period is probably overoptimistic. Let’s rework this evaluation, using a 10 years period instead of 5 for the outsourcing rate to pass from 34% to 75%, the off loading being equally shared by IP vendors and foundries, a questionable assumption (!). The results for 2015 would be:
If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 12%, and a market size passing from $1 677M in 2010 to almost $3 000M in 2015. Amazingly, this CAGR is similar with the result found by Semico (Semico projects this market to continue to grow, exhibiting a CAGR of 12.6% from 2010 – 2015).
This is that we could call a “quick and dirty” analysis, which does not take into account all the effects fueling the growth rate of outsourcing IP, and extend to the overall market (IDM and Fabless) the results validated for the Fabless chip makers. The benefit is to show that, opposite to EDA (except if they can change their business model to increase their product value), the IP market will grow and the CAGR (linked to outsourcing only) can be from 12% to 18% depending at what speed the Fabless and IDM will offload the non strategic part of their design.
Another very interesting point is the fact the foundries are the other beneficiary from outsourcing design IP blocks. This point would request another blog to better understand how the foundries will position this service. Will they act like the FPGA vendors, who have realized for long time now that offering IP is strategic to catch new businesses, and even more to keep their customers captives, but do not necessarily value IP at the right (higher) price? How will the foundries position in respect with the IP vendors, officially their partners? Will they compete with them, considering that IP is a decent source for extra revenue or simply provide IP on a case by case basis? Clearly, they will have to invest even more time to define their IP strategy, and money to develop or acquire the IP function their customer will increasingly need due to outsourcing…
Eric Esteve (www.ip-nest.com)
[post_title] => Source of IP: Silicon foundries provides 18% of Design IP blocks, IP vendors only 16% to Fabless
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[post_content] => The credit here goes to Atrenta for surveying their customer base in an effort to open up new communication channels for in-demand content using Web 2.0 technologies. The results are not surprising to me but they may be to other semiconductor ecosystem executives who do not get Social Media at all!
I have been using LinkedIn for five+ years and consider it one of the most productive tools for the semiconductor industry on a whole. No matter what your job is, if you are not USING LinkedIn for peer-to-peer communications you are not realizing your full professional potential.
Blogs are in fact the most effective form of communication for semiconductor professionals today. The analytics behind blogs also provide important trending data to better understand the markets you serve and the people you work with. Blogging is also the most cost effective branding tool available today: company branding, product branding, and people branding. When I started blogging two years ago I was pretty much invisible. Now I'm branded as an “internationally recognized industry blogger”. Go figure.
I credit Atrenta for promoting blogging in our industry back in July 2009 with a Blogfest at the 46[SUP]th[/SUP] DAC. Here is my blog on it: Blogging From SFO: Beware of Bloggers!A bit dated but still an interesting read. I had just started blogging a couple of months prior. Thank you Mike Gianfagna, Atrenta vice president of marketing, he clearly gets social media. Back when I started, bloggers were not treated as press, and editors did not like us at all. Now bloggers are called NEW MEDIA and treated as well as, if not better than the traditional press. In fact, most of the experienced editors in our industry are now bloggers. Go figure.
Today everything and everyone is connected and crowdsourced. In fact, all social media, from blogs, to forums and wikis have a profound impact on how people communicate, search for information, and make decisions. Research clearly shows that people who share knowledge and personal experience via blogs, forums, and wikis can influence 40-60% of all visitors to a specific course of action. More and more, people will get product information and direction from independent top influencers rather than getting it from vendor sites, advertisements, or other biased sources.
For vendors, social media is no longer an experiment or a moonlighting function. Social media is now an integral part of corporate communications. Unfortunately, vendor direct blogging, tweeting, and forums are all sunshine and no rain which limits the credibility. Vendor direct social media is also all talk and no listen (not crowdsourcing). Social media is all about crowdsourcing and that is just not possible on a vendor specific site.
While Google, Yahoo, Bing, and other search engines will continue to play an important role in social media, peer-to-peer communication sites like the SemiWiki project are the new search. The role of user generated “in-demand” content has changed the way information is exchanged. In contrast to the SALES experience offered by EDA/IP portals, vendor websites, and webinars, SemiWiki brings technology and technologists closer together than ever before, closing the gap between pre-sales expectations and post-sales experience.
5 things you should know about SemiWiki.com:
[LIST=1]
SemiWiki is global. Your experience here will be from around the world with an incredible amount of information at your fingertips. Make sure you connect and interact, make sure you engage at all levels.
Build relationships and network. You can truly connect here with people who you have not met. Make friends and create a support system for your professional life.
Take the good and the bad. Distinguish between fact and opinion, objective and subjective. People will either like or dislike your posts and there is something to be learned from both.
Don’t be evil. Top influencers will have one thing in common, they use their influence for the greater good.
Be yourself.Impersonating others online is a crime so just be yourself. Share your knowledge, share your profession, share your passion, brand yourself. You don’t have to be an expert or industry icon to be a top influencer on SemiWiki.
The goal of SemiWiki is to bring members of the semiconductor ecosystem together and to foster better collaboration in meeting the challenges of advanced semiconductor design and manufacturing. Members of the EDA, IP and foundry ecosystem will contribute meaningful content including wikis, blogs and discussion forums.
"Our industry needs a site that facilitates real time, vendor neutral discussion among real users," said Daniel Nenni, internationally recognized industry blogger and founder of the SemiWiki Project. "SemiWiki.com will provide our members with a connected community that promotes the open exchange of ideas, experiences and feedback."
About the SemiWiki Project
The SemiWiki Project provides in-demand content for semiconductor design and manufacturing, facilitating peer-to-peer communications using Web 2.0 technologies. Daniel Nenni will be joined by industry bloggers Paul McLellan, Daniel Payne, Steve Moran, and Eric Esteve at SemiWiki.com.
[post_title] => Semiconductor Social Networking Survey Results
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There has been a lot of talk about the fluid role of IP in semiconductor design. With the Synopsys acquisition of Virage Logic the playing field has tilted substantially in favor of Synopsys... or maybe not!
At first glance this acquisition appears to be a huge threat to EDA and IP companies allowing Synopsys to “throw in” IP as a value added product/service. But this may be hasty thinking. There are many several reasons to use external IP but at the end of the day it is always an economic decision and that economic decision is made after looking at two sides of a single coin. In absolute terms, is it less expensive to buy rather than build? And which option represents the least amount of risk?
In many cases the risk side of the coin is more important than cost. It might very well be, that a design team or a design manager comes to the conclusion that they “could” build an element in their design for less money than it would cost to acquire it. They might even conclude they could build a better (faster, smaller) device than the one being purchased. But, if purchasing IP allows them to conserve resources by allocating engineering resources to the secret sauce portions of their design it means they will get a lot more bang for their buck. It also turns the IP company into a financing mechanism, by pushing payment for that portion of the design down the road, in some cases pushing it out until actual production begins.
In the short run, it might appear that getting your tools and IP from a single vendor reduces cost and risk. This might even be true looking at a single project, but over time and multiple projects the risk factor becomes huge. Going soup to nuts with a single vendor gives control of your whole design to an outside vendor who does not have the same goals you have. Their goal incentive is not to make your chips better or even to make your company more profitable, but rather to keep you as captive as possible. They have very little incentive to innovate and once you are deeply in their web, there is very little incentive to fix problems rapidly; after all where else can you go?
The solution then becomes multiple IP vendors. It is a healthy long term strategy for both the individual companies and the industry as a whole. It ensures that IP will keep up with technology advancements and negotiation of financial terms on IP will happen on a more or less level playing field. As Eric Esteve and some subsequent posters pointed out in the Semiwiki.com forum discussion The IP Paradox the biggest challenge design managers face is sleuthing out the best IP and the most reliable partner.
For these reasons I believe that you will see the role of IP to become more significant and why simiwiki will be an important part of that equation.
[post_title] => The Looming IP Explosion
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[post_date] => 2011-02-12 17:42:00
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The big EDA news last week of course was the CNBC interview (HERE) with infamous corporate raider Carl Icahn. Carl is not happy with Mentor Executives, nor is Mentor investor Donald Drapkin who said, and I quote, "It's just a sleepy company run like a country club”. Carl and Donald’s combined MENT investment is 20%+ so expect fireworks at the Mentor Graphics shareholder meeting on May 6[SUP]th[/SUP].
Mentor Sleepy Company Country Club data points to ponder:
[LIST=1]
G&A is about the same as CDNS's, apples to apples. Synopsys is more of a pear than an apple.
Revenues AND market shares are increasing in a consolidating market.
From LinkedIn: Mentor Graphics has 35 new job opportunities!
Costs ARE being cut WITHOUT layoffs and other disruptive measures. Wally even flies economy. Seriously, he told me this over drinks. Mentor’s move to the former Avant! building last year both CUT costs and increased space. They even got rid of the creepy bedroom suite with a jacuzzi behind the CEO's (Gerry Hsu's) office.
Here is my message to Carl and his corporate raiding friends:
What in the hell are you thinking? Do you actually know what EDA is? Our market is shrinking, not growing. Since the beginning of time, inorganic growth (acquisitions) is the only way EDA thrives and even that is now threatened by the overly competitive nature of Synopsys, the lack of investment by the venture capital community, and now FPGA companies are buying EDA start-ups for premium revenue multiples (Xilinx recently bought AutoESL @ 50x revenue?)
Listen Carl, the semiconductor design and manufacturing ecosystem is just that, an ecosystem. Disrupting Mentor in this fashion could upset the balance of nature and it could all come crashing down. Even if you are successful in the boardroom coup, who is going to buy Mentor Graphics? Even if you carve it up like a turkey.
There are no competitors strong enough to buy Mentor’s most profitable turkey parts. Synopsys is the only EDA company with a bankroll large enough. Fortunately, Synopsys holds either the #1 or #2 market position in every semiconductor design segment so what is their motivation to buy a Mentor drumstick or wing? Synopsys also has an ego larger than EDA itself and has been competing head-to-head with Mentor since birth. Buying the Calibre franchise would be admitting DRC defeat and that is just not part of the Synopsys ultra competitive culture.
What about Cadence? There is even worse history there. Remember when Cadence tried to buy Mentor and Mentor returned the favor by trying to buy Cadence? That was Cadence CEO Mike Fister’s Waterloo. Even if Cadence billionaire CEO Lip-Bu Tan could raise the money for Mentor turkey parts, the company integration would be a nightmare. Wrapping the Cadence culture around Mentor would not work.
One corporate raidering possibility is a foundry buying Mentor parts. TSMC and GlobalFoundries have the money and competitive spirit to do so, but the top fabless semiconductor companies might not care for that at all. Bringing semiconductor design full circle with tools coming directly from the semiconductor manufacturers? Is that really what we want to do here? It is much more likely that GlobalFoundries buys the physical IP division of ARM for $1B+. Now that’s what I call collaboration!
As a result of all this drama, Mentor has retained Goldman Sachs “to explore the company strategic options”. Hopefully this is just a play to silence Carl and friends, I really do not want Mentor dissected.
Here is my message toMentor:
Take over Cadence or Magma already! My Mentor/Cadence/Magma merger BLOG last year was THE most viewed blog of 2010 for a reason, people want it to happen. Synopsys is an EDA/IP MONOPOLY and something must be done! If any of you folks out there do not agree, look up the word delusional.
REGISTER 4 EDA TECH FORUM HERE!
[post_title] => Mentor Graphics Should Be Acquired or Sold: Carl Icahn
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[post_content] => A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan
Today’s IC designs are complex. They contain vast arrays of features and functionality in addition to multiple power domains required to reduce power consumption and improve design efficiency. With so much going on, design verification plays an important role in assuring that your design does what you intended.Often, verification will include simulations (for functional compliance), and extensive physical verification (PV) checks to ensure that the IC has been implemented correctly, including DRC, LVS, DFM and others. A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.
To address these types of design errors, electrical rule checking (ERC) has seen significant growth in recent years. Teams developing submicron, mixed-signal, or low-power devices used in mobile and other applications are particularly concerned about advanced ERC. This concern has lead to investments by circuit designers, CAD engineers, design project managers, verification engineers, and process modeling engineers to increase coverage, and by the EDA tool vendors to enable advanced checks and make describing the rules simpler. The investment has a large ROI because robust ERC reduces the number of die susceptible to catastrophic electrical failures during final testing, as well as premature failures in the field.
Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need for a highly flexible, user-configurable tool. ERCs are important, but particularly challenging in designs with multiple voltage domains and mixed analog/digital circuits, such as low-power devices targeting mobile and other battery-powered applications.
Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are difficult to identify in the simulation space or with traditional PV techniques. Often these subtle errors don’t result in immediate part failure, but performance degradation over time. Effects such as Negative Bias Temperature Instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates [1] [2] [3], and Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over time [4]. Soft breakdown (SBD) [4] also contributes as a time-dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown.
Some electrical rule checks are based on the netlist and include looking for floating devices, nets, or pins, detecting thin gates connected to excessive voltages, checking for violations of the maximum allowed number of series pass gates, and finding issues related to level shifter designs. Other checks are performed using geometric layout information, such as net area ratios for antenna rules, floating wells, and minimum “hot” NWELL width.
Topological ESD check:Device gates connected to I/O pads should be protected by resistor and turn-off MOS device.
An important application of ERC is verifying that electrostatic discharge (ESD) protection circuits are in place wherever the device is vulnerable, whether those circuits are included in the schematic and netlist or not. To ensure a robust design, the ERC tool must go beyond simple schematic or netlist-to-layout verification and recognize where ESD protection elements are needed, based on combined information from the netlist and the layout topology.
In multiple power domains, other precautions have to be considered. For example, IP reuse may require more robust rules to avoid device burnout at the system integration stage. This is particularly the case where an IP block is being re-targeted to a different process node or power domain [1]. The introduction of lower voltage power domains is also an area where IP reuse and the contribution to the overall reliability of the chip must be considered. Often, to attain lower voltage thresholds for lower power circuits, the oxide layer of a transistor is made thinner. While this has significant voltage and power benefits, there are areas of concern. One of these is when thin-oxide gates have paths to specific voltage rails. To avoid long term damage to the gate over a period of time, which results in performance degradation, the voltage rail must be carefully chosen. A previous implementation may have the gate tied at a voltage that is too high for the current use.
Successful integration of physical IP blocks requires knowledge of the design hierarchy as well as the structure of voltage domains and cell voltage constraints. Design hierarchy also comes into play when one set of rules is applied to upper layer interconnects and pad frames, while different rules are applied between blocks crossing multiple power domains.
In the figure below, we can see results from a check to verify that a signal net from one power domain does not directly cross into another. In this case, we would probably expect a level shifter or some other protection circuit to allow the safe passage of a signal from one power domain to another.
Topological ERC example that needs circuit identification programmable entry. Advanced ERC: Serially connected gates cannot be on different supplies or grounds.
As ERC becomes more critical to producing a reliable product, designers and engineers are constantly discovering new checks that they would like to make during verification. These checks are based on their accumulated knowledge and best practices of design groups; thus, there is no “standard” set of checks. Consequently, it is crucial that an ERC tool be easily programmable, allowing users to adapt it quickly to new checks as they become needed.
As an example of advanced ERC, the circuit below shows PMOS and NMOS thin-oxide gates with direct and indirect connections to power the domains VDD2 and VSS2. An indirect connection may be through another transistor, diode, resistor, or other circuit elements. These connections often form the basis of “missed” paths that are not readily identified during design reviews. This is particularly true if the indirect path is through a circuit elsewhere in the design hierarchy that is not obvious. The local power connections in the sub-circuit itself (VDD/VSS) are seen in the context of the larger design. The external connections to an otherwise verified IP block must be evaluated.
To show how designers can use new ERC verification tools we provide an example check based on Mentor Graphics’ Calibre® PERC product, which can be used to find design errors not identified by traditional PV tools. Typically Calibre PERC is used in combination with Calibre nmLVS allowing users to run multiple electrical rule checks independently or together, using either standard rules from the foundry, or their own custom rules. Users can insert electrical rule checks into their design flow with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in SVRF and the TCL-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.
To identify thin-oxide gates at risk, designers could define a check in Calibre PERC expressed in pseudo code here for simplicity:
1) Identify power domains in the design
2) Identify which power domains are “not safe” for thin-oxide gates
3) Identify the specific device types and subtypes that corresponding to thin oxide MOS devices
4) Check the related “source”, “drain”, or “bulk” pin connection on these thin-oxide MOS devices to power domains
a) Evaluate both direct and indirect paths
b) Flag an error for this-oxide MOS connections that are to “not safe” power domains
In complex systems, it is not uncommon to have multiple power domains, which require complex design rules to determine which domains are safe, and under what conditions.
Thin-oxide gates with direct and indirect paths to VDD2/VSS2. These connections are made outside the sub-circuit.
Verification of bulk pin connectivity is particularly import for determining if a circuit is susceptible to these time related reliability issues. As shown below, an incorrect bulk connection may make this PMOS gate vulnerable to NBTI due to a high bulk voltage.
A Thin-oxide PMOS (Model: mos_lv) with a path to high voltage may lead to NBTI susceptibility
To learn more about reliability checking, download the white paper "Addressing Reliability and Circuit Verification Challenges with Calibre® PERC". Also, visit my personal blog at http://blogs.mentor.com/matthew_hogan/.
References
[1] Hamed Abrishami, et. al., “NBTI-Aware Flip-Flop Characterization and Design”, GLSVLSI’08, May 4–6, 2008
[2] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” Electron Device Letter, vol. 26, no. 8, pp. 560-562, Aug. 2005.
[3] Hong Luo, et. al., “Modeling of PMOS NBTI Effect Considering Temperature Variation”, 8th International Symposium on Quality Electronic Design (ISQED'07)
[4] Jin Qin, et. al., “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI”, 2007 IIRW FINAL REPORT
[post_title] => New ERC Tools Catch Design Errors
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[post_content] => 
Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already know.
Their top attraction is Cadence (buy rating, with a price target of $13), followed by Synopsys (buy rating, with a price target of $35) and then Mentor (neutral, with a price target of $15).
My comments: Synopsys is clearly the EDA leader but as the largest company it is hard for them to grow faster than the overal EDA market. Cadence is in year 3 of a transition and the interesting thing to watch will be how much business they have in year 3 because historically these transitions risk doing 3 years of business in 2 years leaving thin pickings for the 3rd year (and so a temptation to do some non-ratable business to make the number).
Mentor, for those of you not following along at home, has Carl Icahn nipping at their heels. He has taken a 15% stake in the company and, last week, on CNBC accused them of being a country-club and that they should be sold or broken up. At the very least it should be a good spectator sport. The Merrill Lynch report doesn't mention Icahn and the potential upside/risk.
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[post_title] => EDA and Wall Street
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[post_date] => 2011-02-10 12:42:00
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[post_content] => When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor: Walker, Darryl Gene)
DRC+
Today with the dominant fab-light model most IC designers need to work with a foundry to receive DRC decks plus DFM rules and guidelines.
Because DRC complexity have exploded to over 1,000 rules at the 65nm node and below, we must consider new techniques like 2D pattern-matching to speed up the checking.
DFM
Design For Manufacturing now covers multiple EDA tools, even Place & Route. The width of interconnect is now dependent on adjacent wires in two dimensions:
CMP
Chemical Mechanical Polishing is commonly used to make IC layouts more planar, which improves yield by keeping the layers parallel to the substrate. There are IC layout rules to ensure that CMP will work properly.
(IC cross-section. Left: Without CMP, Right: With CMP)
Variability
Drawing a transistor gate as a rectangle isn't how it really ends up in silicon. By providing feedback to the circuit designer on how the non-ideal transistor will perform, it gives a more accurate way to simulate circuit performance.
On March 10 in Santa Clara at the EDA Tech Forum you can meet and learn from experts in these topics of: DRC+, DFM, CMP, Variabiity
This is an all-day seminar, and best of all the price is free. Just visit the site and register online to reserve your spot.
[post_title] => DRC+, DFM, CMP, Variablility
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[post_content] => "Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO
Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address these challenges seems less clear. Strategies to optimize the chip implementation flow, including approaches such as transistor-level optimization abound. While these techniques contribute to the solution, they all miss the primary force of design evolution. Over the past 30 years or so, it has been proven time and again that moving design abstraction to the next higher level is required if design technology is to advance. In this keynote presentation, a new EDA model will be presented, examples of past trends will be identified, and an assessment will be made on what these trends mean in the context of the current challenges before us. A snapshot of the future will be presented which will contain some non-intuitive predictions.
The talk basically looks at semiconductor design and EDA from a historical perspective and highlights that things always move to a higher level of abstraction to address complexity. IP was the most relevant example used as it continues to have a profound impact on the semiconductor design manufacturing ecosystem. You will be hard pressed to find a modern semiconductor design, in production today, without a reusable block, whether commercial or proprietary.
In fact, commercial semiconductor IP revenue jumped 30%+ in 2010, according to EDAC, and soft (abstracted) IP is a significant part of that number. Interestingly, semiconductor IP growth tracks nicely with semiconductor industry growth (30%+) and not EDA revenue growth (0%). Take a look at the SIP and EDA business models and you will see why (semiconductor IP is success based and EDA is not).
The talk also focused on platform based design and IP reuse as critical items to tame complexity and spiraling design cost. Ajoy then talked about a "new breed" of EDA company - called "5th generation EDA" to address these requirements. Check out the Atrenta newsletter HERE, it is a company you definitely want to watch!
[post_title] => Keynote Address at the 16th Asia and South Pacific Design Automation Conference
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[post_date] => 2011-02-03 14:34:00
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[post_content] => 
During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!
According to Morris Chang:
“For 2011, we expect the overall semiconductor market excluding memory to grow by about 7%.”
I still say 7% is low and hold to my double digit prediction for semiconductor growth in 2011. New phones, tablets, and communications products will continue to drive semiconductors this year and next.
“We expect the foundry market to grow by about 15%, and we believe TSMC will grow more than 20% in U.S. dollars.”
On the previous conference call Morris Chang predicted 14% growth for TSMC in 2011. In my follow-up blogs I predicted 20%+ 2011 growth for TSMC. Morris and I are now aligned so my prediction stands, TSMC will again post incredible numbers in 2011.
“I want to say a few words about the 450-millimeter wafer manufacturing. Our first 450-millimeter pilot line is planned at our Fab12 Phase VI, starting with 20-nanometer technology. The timing of pilot line will be around 2013, 2014. Our first 450-millimeter production line is planned in around 2015, 2016,” said Morris Change, chief executive officer and chairman of TSMC
This is déjà vu of the 200mm to 300mm transition. There was endless debate and lots of 300mm doubters until TSMC put a stake in the ground and started building the first 300mm fab. TSMC, Intel, Toshiba, and Samsung all publicly support the transition to 450mm citing both important technological advancements as well as significant capacity increases to meet the needs of future smartphone and tablet users around the world. One 450mm wafer should yield more than twice as much compared to today’s 300mm, and well over four times the number from yesterday’s 200mm.
Unfortunately, once scheduled for a 2012 launch, the transition to 450mm wafers has been delayed due to both doubters and the financial meltdown. In 2009, the semiconductor equipment manufacturers, the enablers of 450mm wafers, lost more than $1B and released 30%-40% of their workforces. But with the current semiconductor industry upswing with foundries like TSMC and UMC operating at maximum capacity, 450mm semiconductor manufacturing is now in sight.
GlobalFoundries is the last public 450mm foundry doubter. According to Thomas Sonderman, Vice President of manufacturing systems and technology at GlobalFoundries:
“The rush to 450mm suggests a lack of ideas for improving fab productivity. At GlobalFoundries, we see a tremendous amount of headroom left in the 300mm process. We are tapping our expertise in lean manufacturing to extend the lifecycle of the industry’s current 300mm ….”
In my opinion this is one of the main drivers for TSMC and 450mm, the GlobalFoundries challenge. It has definitely raised the innovation bar for TSMC and they have reacted accordingly. TSMC will build a 450mm fab and the semiconductor equipment manufactures will accommodate their most valued customer, believe it. Look for the FabClub (GlobalFoundries, Samsung, and IBM) to announce 450mm fabs in the coming months as they have no other choice if they want to compete with TSMC.
[post_title] => TSMC Raises The Semiconductor Bar With 450mm!
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[post_date] => 2011-02-01 13:38:00
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[post_content] => Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital flow. No more foucs on just point tools, instead we're organized end to end flow based. Top 3 of best tool innovations at DesignCon (nominated).
Challenges (2) – Japanese key customers confirm the needs. How to get faster ARM cores, .8 to 1GHz.
Low Power, Mixed Signal – more automation (power shutoff, dynamic voltage scaling), tool interoperability
Adv tech – 3D, 20nm. How to make mobile video? There are node Migration risks.
3. Traditional tools are breaking, convergence issues (Physical synthesis), The 3D tool flow is very different from previous tool flows. Abstraction models at chip and package levels are new.
4. Intent-abstraction-convergence. Supports 28nm flow. Faster P&R (2x). New power intent architect (graphical UI), shipped in December.
Abstraction (patented) – gate level netlist analysis with logic and physical, compress db size of 80%, stores more efficiently. Renesas paper has numbers on db size. Hierarchical modeling of IP for power budget.
Convergence – Physical synthesis, ECO flow improvements to reduce the rework back into RTL. Promote an all-Cadence tool flow.
Litho hot spots, how to fix? In the past simulation approaches to litho with long run times. InDesign DFM from Clearshap a few years ago. DRC+ is a new technique with pattern-based, see Global Foundries press release. DFM and Litho is not an afterthought, using DRC+ and InDesign together.
Q: How does this compare to Mentor's approach of DFM in the loop?
A: No comment on Mentor.
IC (Virtuoso), Package (Allegro) - all play together for 3D design.
Mixed-signal – how to do timing? Build macros. Tool now on the fly can traverse digital and do STA, mixed-signal optimization is done on the fly. Analog is still transistor-level optimization.
5. How to design 3D and analyze. 3D config file ties all the domains together. Beyond just 2 to 3 die stack, expect 7 stacks. Concurrent design now possible. Allegro shows the 3D view for 3D design. Interposer example has multiple routing levels in it. Foundries have new design rules (TSMC, Global Foundries) for 3D.
Thermal plot showing 2D and 3D views of gradients. Thermal results fed back to timing.
Q: How does this compare to Gradient DA or Apache DA?
A: No comment on competition.
6. ARM relationship, they used a Cadence flow. Out of box scripts, use Cadence services to increase the CPU core speeds.
8. Customer feedback
Q: Summary – can I still use OpenDoor partners?
A: Yes, We have a framework with OA, and CPF standards.
3D white paper is available.
DRC+ paper with Global Foundries
[post_title] => DesignCon 2011 Trip Reports!
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[post_content] => Thanks to the Semiconductor Ecosystem Survey from GSA-Wharton and the key indicators of semiconductor companies’ technology strategies related to IP:
- IP Reuse: On average, a fabless semiconductor company reuses about 63% of design IP in the revision of an existing product design and about 44% in a new product design.
- Source of IP: Silicon foundries are becoming an important source of design IP for fabless companies in addition to third-party IP firms. On average, 18% of design IP blocks are from the foundry's portfolio/library, followed by 16% for third-party licensing firms.
The other key indicators are about differentiation and time-to-market.Let’s make some comments. First of all, as I am focusing on IP… I am happy, as the report clearly links IP as one of the major source of innovation. But, when I think to my blogger colleagues who’s focus is on EDA (namely, Dan Nenni, Daniel Payne and Paul McLellan), I think they have good reasons to be disappointed, as within the 26 pages you will never found the mention of EDA. The report is dealing about “Innovation”, “partners” and “ecosystem”, referring to the fables companies, so –intentionally or not- deciding to omit EDA companies in the ecosystem looks strange to me… Let’s come back to IP. The number of design IP blocks coming from foundries (18%) is higher than these coming from the IP vendors (16%). Is it a surprise? No, as when looking at the list of IP offered by the major foundries, you realize that this list is pretty long, even if we can qualify these IP as commodities in most of the cases. Yes if you consider the large number of IP vendors (more than 460 listed on D&R). They have to offer differentiated products to compete with their foundry partners! The other figure, 66% of design IP blocks are being internally sourced by the fabless, certainly opens a growth opportunity for the IP “providers” (foundry or IP vendor). We all know that the trend is, and will be, to outsource more design IP blocks, with a limit defined by the fabless themselves: you don’t want to outsource the part of the design on which you build your differentiation. We can guess that these differentiating functions represent a lot less than 66% of the design blocks. The real number is probably in the 20 to 30% range, say 25%, arbitrary. Now, the question is to know how long it will take for the fables to move from 66% down to 25% of internally reused IP blocks: 5 years? 10 years? Let’s look at these two scenarios and forecast the effect on the IP market size growth rate. In one case, the IP market would move from 16% (of design blocks) to 37% in 2015 (assuming the outsourcing is equally shared by the IP vendors and the foundries, which is certainly not right, but the “less wrong” assumption we can make here). If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 18%, and a market size passing from $1 677M in 2010 to $3 850M in 2015.But we know that many other effects can generate the growth: the emergence of new protocols is pushing the fabless or IDM to outsource the function, because it is too complex to design, or require competencies not available within the company. The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP. Or new functions issued from innovation, which simply did not exist before, and have to be licensed to the inventors (HDMI is a good example). This to say that the size of the market will be larger than that we have found by only using the growth of outsourcing rate! This 18% CAGR is impressive, especially when you consider the other growth factors for the IP market: · The emergence of new protocols, pushing the fabless or IDM to outsource the function, because it is too complex or too long to design, or require competencies not available within the company.· The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP.· Or to integrate new functions issued from innovation, which simply did not exist before, when the shortest path is to licensed it, to the inventors or IP vendors (HDMI is a good example).This to say that the market size should be larger than that we have found by only using the growth of outsourcing rate, so the assumption based on a 5 years period is probably overoptimistic. Let’s rework this evaluation, using a 10 years period instead of 5 for the outsourcing rate to pass from 34% to 75%, the off loading being equally shared by IP vendors and foundries, a questionable assumption (!). The results for 2015 would be:
If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 12%, and a market size passing from $1 677M in 2010 to almost $3 000M in 2015. Amazingly, this CAGR is similar with the result found by Semico (Semico projects this market to continue to grow, exhibiting a CAGR of 12.6% from 2010 – 2015).
This is that we could call a “quick and dirty” analysis, which does not take into account all the effects fueling the growth rate of outsourcing IP, and extend to the overall market (IDM and Fabless) the results validated for the Fabless chip makers. The benefit is to show that, opposite to EDA (except if they can change their business model to increase their product value), the IP market will grow and the CAGR (linked to outsourcing only) can be from 12% to 18% depending at what speed the Fabless and IDM will offload the non strategic part of their design.
Another very interesting point is the fact the foundries are the other beneficiary from outsourcing design IP blocks. This point would request another blog to better understand how the foundries will position this service. Will they act like the FPGA vendors, who have realized for long time now that offering IP is strategic to catch new businesses, and even more to keep their customers captives, but do not necessarily value IP at the right (higher) price? How will the foundries position in respect with the IP vendors, officially their partners? Will they compete with them, considering that IP is a decent source for extra revenue or simply provide IP on a case by case basis? Clearly, they will have to invest even more time to define their IP strategy, and money to develop or acquire the IP function their customer will increasingly need due to outsourcing…
Eric Esteve (www.ip-nest.com)
[post_title] => Source of IP: Silicon foundries provides 18% of Design IP blocks, IP vendors only 16% to Fabless
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Thanks to the Semiconductor Ecosystem Survey from GSA-Wharton and the key indicators of semiconductor companies’ technology strategies related to IP:
- IP Reuse: On average, a fabless semiconductor company reuses about 63% of design IP in the revision of an existing product design and about 44% in a new product design.
- Source
…
Read More
The credit here goes to Atrenta for surveying their customer base in an effort to open up new communication channels for in-demand content using Web 2.0 technologies. The results are not surprising to me but they may be to other semiconductor ecosystem executives who do not get Social Media at all!
I have been using LinkedIn for five+… Read More
There has been a lot of talk about the fluid role of IP in semiconductor design. With the Synopsys acquisition of Virage Logic the playing field has tilted substantially in favor of Synopsys… or maybe not!
At first glance this acquisition appears to be a huge threat to EDA and IP companies allowing Synopsys to “throw in” IP as… Read More
The big EDA news last week of course was the CNBC interview (HERE) with infamous corporate raider Carl Icahn. Carl is not happy with Mentor Executives, nor is Mentor investor Donald Drapkin who said, and I quote, “It’s just a sleepy company run like a country club”. Carl and Donald’s combined MENT investment is 20%+ … Read More
A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan
Today’s IC designs are complex. They contain vast arrays of features and functionality in … Read More
EDA and Wall Streetby Paul McLellan on 02-11-2011 at 1:25 pmCategories: EDA
Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already… Read More
When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor:… Read More
"Managing increasing complexity through higher-level of abstraction: What the past has taught us about the future" Dr. Ajoy Bose, Atrenta CEO
Here is the abstract:
Time to market and design complexity challenges are well-known; we have all seen the statistics and predictions. A well-defined strategy to address … Read More
During the most recent conference call (transcript), TSMC not only beat revised estimates and announced record spending levels for 2011, Morris Chang also officially announced that a 450mm fab (Fab 12 Phase VI) is currently in the planning stages with target production @ 20nm in 2015. This is HUGE!
According to Morris Chang:
“For… Read More
Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital… Read More
ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC eraI was asked to give a talk at…Read More
HFSS – A History of Electromagnetic Simulation InnovationIn the 155 years since James Clerk Maxwell…Read More
Podcast EP4: Can China Really Become Self-Sufficient in Semiconductors?