In the semiconductor design industry, most of the designs are created and optimized at the RTL level, mainly through home grown scripts or manual methods. As there can be several iterations in optimizing the hierarchy for physical implementation, it’s too late to do the hierarchical optimizations after reaching the floor plan… Read More
CEO Interview: Khaled Maalej, VSORA Founder and CEOKhaled Maalej is founder and CEO of VSORA,…Read More
Soitec Delivers the Foundation for Next-Generation InterconnectsSoitec is a unique company that is at…Read More
Electrical Rule Checking and Exhaustive Classification of ErrorsThe goal of SoC design teams is to…Read More
Early SoC Dynamic Power Analysis Needs Hardware EmulationThe relentless pursuit for maximizing performance in semiconductor…Read More
Semidynamics Shakes Up Embedded World 2024 with All-In-One AI IP to Power Nextgen AI ChipsSemidynamics takes a non-traditional approach to design enablement.…Read More
Cadence and Reverse Debugging
I wrote back in March about Undo Software. They have a reverse debugging solution called UndoDB (the DB is for debug, not database). I have a soft spot for reverse debugging ever since seeing one of the engineers at Virtutech type reverse single step and seeing the code back up a single instruction and realizing that literally months… Read More
Crossfire – Your partner for IP development, what’s new?
As the SoCs and IPs grow in sizes and complexities, the number of formats, databases, libraries of standard cells and IOs also increase. It becomes a clumsy task to check every cell in a library, its consistency among various format with respect to functionality, timing, naming, labels and so on, and its complex physical properties… Read More
Synopsys Earnings
The perfect quarterly results are to slightly beat the consensus for earnings and profit, and not say anything negative about guidance for the upcoming quarter. Synopsys delivered all that with their latest quarter yesterday. Revenue was $521M versus $483M last year, giving solid growth of over 8%. Non-GAAP earnings per share… Read More
Develop High Performance Machine Vision in the Blink of an Eye
The growing capabilities of silicon along with improved algorithms means that machine vision is becoming increasingly important since more and more systems can be built in such areas as manufacturing, intelligent traffic management, bar code scanning, counterfeit detection and even sports simulation. Is that a 3X driver?… Read More
Substrate coupling analysis method and tool
There has been a lot written on this topic, and some expensive tools proposed to solve this issue, but it is still a concern and a mystery for many designers. The point is that whatever efforts you do, the substrate is common to an entire chip and can cause some undesired coupling if not managed properly and at an early stage. As a start… Read More
EDA Ice Bucket Challenge!
In case you have not heard, the Ice Bucket Challenge is a social media program aiming to increase the awareness of ALS (Amyotrophic lateral sclerosis AKA Lou Gehrig’s Disease). One of our neighbors recently passed away as a result of ALS so this challenge is dedicated to Barbara Letts. After hearing about the challenge my daughter… Read More
Silvaco News: Silicon Valley, China and Korea
Silvaco is one of the sponsors of the GSA Executive Forum to be held over in VC Land at the Rosewood Sand Hill on September 10th. Note that it starts at 11.45am with a networking lunch.
- The featured keynote speakers are Fareed Zakariah and Rana Faroohar, both of CNN. Rana is also Senior Managing Editor of Time.
- The first panel session
USB 3.0 IP on FinFET may stop port pinching
Sometimes a standard is a victim of its own success, at least for a while as the economics catch up to the technology. When a standard like USB 3.0 is announced, with a substantial performance increase over USB 2.0, some of the use cases come on board right away. Others, where vendors enjoy a decent ROI with good-enough performance,… Read More
Vlang – Opportunities Galore for Productivity & Performance
Yes, verification technologies are open to innovation for improved productivity and performance in the face of ever growing SoC/IP design sizes and complexities. There is not much scope left in processor speed to improve, other than multi-core processors in servers which again need software properly architected to be thread-able… Read More
Real men have fabs!