One announcement that I missed coming up to the Design Automation Conference last week was that SiCAD is hosting a portfolio of IBM’s design automation tools in the cloud. Supposedly these are priced half the cost of similar capability from Cadence, Synopsys and Mentor. So should the big three be worried? Is this an earth-shattering… Read More
Jitter: The Overlooked PDN Quality MetricBruce Caryl is a Product Specialist with Siemens EDA…Read More
CEO Interview with Vamshi Kothur, of Tuple TechnologiesIt was my pleasure to meet with Vamshi…Read More
Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCsWhat if you could reduce power and extend…Read More
Reachability in Analog and AMS. Innovation in VerificationCan a combination of learning-based surrogate models plus…Read More
Solido Has Perfected the Emerging EDA Company Business Model!
Last year at #51DAC we gave away more than a thousand printed versions of our book “Fabless: The Transformation of the Semiconductor industry.” This year we gave away pens with a light and stylus. My friends at Solido Design gave away 600 pens in their booth and we gave away another 400 at our DAC reception on Wednesday night. Solido… Read More
Can FD-SOI Change the Rule of Game?
It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from… Read More
Semiconductor Equipment: the Report and the Show
Somebody said to me recently that SEMICON West, which takes place in San Francisco July 14-16th, isn’t that big a deal since very little manufacturing goes on in the US any more. In fact 15% of manufacturing capacity is in north america (I think that actually means the US since I don’t think there are any fabs in Canada).… Read More
The Best Conversations You Missed at #52DAC!
The CEO Fireside Chats were my very favorite part of #52DAC. Dr. Walden Rhines, Lip-Bu Tan, and Dr. Aart de Geus are heroes of the EDA industry, absolutely. I saw all three Fireside Chats and the one word that I’m left with is INSPIRED! … Read More
DDR stands for Don’t Do (Just) RTL
In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More
Apple Watch Design Revisit with a Wi-Fi Twist
Apple Watch is the world’s most celebrated gadget in 2015. At the same time, however, early product reviews highlight some issues about slow apps, less than impressive user experience, and short battery life.
Apple, the master of artful integration, has done well for its reputation of elite hardware and has been able to … Read More
New Tool Suite to Accelerate SoC Integration
Today, an SoC is seen in the context of an optimized assembly of IPs; it’s no more a single monolithic chip design. It’s very common to see an ARM processor IP along with an interconnect IP, a memory IP, and couple of buses and interfaces IP in an SoC. Although the SoC seems to be an integrated collection of IPs, it can be very complex and… Read More
High Level Synthesis. Are We There Yet?
High level synthesis (HLS) seems to have been part of the backdrop of design automation for so long that it seems to be one of those things that nobody notices any more. But it has also crept up on people and gone from interesting technology to keep an eye on to getting genuine adoption. The first commercial product in the space was behavioral… Read More
Further Delays for Intel 10nm?
Intel’s 10nm may be reliving the 14nm elongated delay issue-
Schedules & tool delivery may be pushed even deeper into 2016-
Meanwhile Samsung & TSMC press on-
Could Intel be embarrassed?
… Read More
Facing the Quantum Nature of EUV Lithography