Go off and do something wonderful,” said Robert (Bob) Noyce, co-founder of Fairchild semiconductors and Intel Corporation. He was heard, and the quality of our lives has been elevated by the wonderful pursuits of skilled pioneers. Notice that Bob did not say, “Go off and become great leaders.” This is because great leaders of the… Read More
AI Booming is Fueling Interface IP 23.5% YoY GrowthAI explosion is clearly driving semi-industry since 2020.…Read More
Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC VerificationIn the race to deliver ever-larger SoCs under…Read More
Arteris Simplifies Design Reuse with Magillem PackagingMany know Arteris as the “network-on-chip”, or NoC,…Read More
Delivering Zero Defect Products – EVS Testing
Competition in the semiconductor product marketplace has grown increasingly difficult as suppliers constantly search for ways to differentiate their products. Customers expect low cost, problem-free product performance. Automotive manufacturers in particular expect zero defects as field failures can prove very costly.… Read More
Shifting Low Power Verification to an IP to SoC Flow
One of the most exciting recent developments in low power design and verification is the successive refinement flow developed by ARM® and Mentor Graphics®.… Read More
Do 8 Cores Really Matter in Smartphones?
As the smartphone industry has begun to mature, one-upmanship among smartphone manufacturers and SoC vendors has bred a dangerous trend: ever-increasing processor core counts and the association between increased CPU core count and greater performance. This association originated as SoC vendors and OEMs have tried to find… Read More
To err is runtime; to manage, NoC
Software abstraction is a huge benefit of a network-on-chip (NoC), but with flexibility comes the potential for runtime errors. Improper addresses and illegal commands can generate unexpected behavior. Timeouts can occur on congested paths. Security violations can arise from oblivious or malicious access attempts.
Runtime… Read More
Are FinFETs too Expensive for Mainstream Chips?
One of the most common things I hear now is that the majority of the fabless semiconductor business will stay at 28nm due to the high cost of FinFETs. I wholeheartedly disagree, mainly because I have been hearing that for many years and it has yet to be proven true. The same was said about 40nm since 28nm HKMG was more expensive, which … Read More
SpyGlass World 2015 User Group Meeting
I attended SpyGlass World this week – to give you an update, to catch up with old friends, including users, and to meet some of the new (to me) players from the Synopsys side of the event. The event was held in the United Club at Levi stadium, just like last year. Don’t know if this will continue. Merging the SpyGlass User Group into SNUG… Read More
GlobalFoundries 14nm Process Update
Last Monday Daniel Nenni and I had a conference call with Jason Gorss and Shubhankar Basu of Global Foundries to get an update on their 14nm process. Shubhankar is the product line manager for 14nm.
Global Foundries 14nm process is a FinFET on bulk process they licensed from Samsung and both companies supply the same process although… Read More
How to Make Smartphone Even Smarter? With Deep Learning
The IT industry marvels like augmented reality and artificial intelligence, which marked technological utopianism in the science fiction movies during the 1970s and 1980s, are here now, enabled by a machine-learning technique called deep learning.… Read More
Free Copy of EDAgraffiti!
Last month we offered a free PDF version of our book “Fabless: The Transformation of the Semiconductor Industry”, for the greater good. More than thirteen thousand people have downloaded it thus far so we would like to keep the momentum going with another book giveaway. Paul McLellan has graciously offered his book… Read More
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