Synopsys launch BTLE PHY IP, qualified by the Bluetooth Special Interest Group (SIG) and meeting compliance with the Bluetooth® Smart v4.2 specification. The company has built a partnership with Mindtree to provide a complete solution, integrating Synopsys’ Bluetooth Smart PHY IP and Mindtree’s production-proven BlueLitE… Read More





Explore Google Chromium USB Type-C example designs using GoArks USB – C Thru
One of the early adopters of USB Type-C and USB Power Delivery is Google for their Chromium projects. More interestingly Google shared the complete design of the USB Type-C products in public domain right from schematic to source code of the solutions. This article explores how to use USB C-Thru board to explore Google’s designs… Read More
Where is the Money in IoT?
As we all know IoT (Internet of Things) is the “next big thing” across many different industries including the fabless semiconductor ecosystem. The first recorded IoT blog on SemiWiki was in 2014 and currently we have 173 IoT blogs posted that have earned more than 600,000 views and counting. So yes, IoT is the next big thing, absolutely.… Read More
Design units come to faster Riviera-PRO release
For the latest incremental improvements to its Riviera-PRO functional verification platform, Aldec has turned to streamlining random constraint performance. The new Riviera-PRO 2016.02 release also is now fully supported on Windows 10 and adds a new debugger tool.… Read More
Verdi Update and NVIDIA on Verification Compiler
Synopsys hosted a lunch session on Thursday of DVCon. Michael Sanie of Synopsys opened the session, with a look back at the last DVCon where he had talked about Verification Compiler (VC) and extending the platform to Verification Continuum, which adds emulation and FPGA-based prototyping (HAPS – there was a very cool HAPS demo… Read More
Intel Adds ‘Authenticate’ Multi-Factor Security Feature
Last summer, Intel launched their 14nm, 6th Generation Core processors, code-named ‘Skylake’, alongside Microsoft’s new Windows 10 operating system. As things usually go in the enterprise world, the commercial 6th Generation of Intel’s Core vPro processors weren’t too far behind with increased security and manageability… Read More
Intel EUV Photoresist Progress and ASML High NA EUV
SPIE Days 3 and 4:
Anna Lio of Intel presented EUV resists: What’s next?
Intel wants to insert EUV at 7nm but it has to be ready and economical. Critical Dimension Uniformity (CDU), Line Width Roughness (LWR) and edge placement/stochastics are all stable on 22nm, 14nm and 10nm pilot lines.… Read More
Mentor at DVCon – Visualize This
Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor platform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.
On a more technical note, he showed us a familiar survey they had completed with the… Read More
Cadence is again the best EDA company to work for!
We wrote about the history of Cadence in preparation for our book “Fabless: The Transformation of the Semiconductor Industry” in 2012. EDA played a key role in enabling the fabless semiconductor revolution and Cadence was right there at the beginning. Famed EETimes editor Richard Goering helped us with the book and the Cadence… Read More
Creating a better embedded FPGA IP product
Our introduction to Flex Logix and its embedded FPGA core IP drew several comments, predominantly along the lines of a few things like this have been tried before. In this installment, we dive into the EFLX cores, the FPGA toolchain, the roadmap, and a powerful integration feature.… Read More
Why I Think Intel 3.0 Will Succeed