Synopsys Webinar – Enabling Multi-Die Design with IntelAs we all know, the age of multi-die…Read More
Materials Selection Methodology White PaperThe Granta EduPack White Paper on Materials Selection,…Read More
Formal Verification: Why It Matters for Post-Quantum CryptographyFormal verification is becoming essential in the design…Read More
Architecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem RealitiesDesigning a system-on-chip (SoC) has never been more…Read More
More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More
GLOBALFOUNDRIES has been evangelizing their 22FDX FD-SOI process for a few months; readers may have seen Tom Simon’s write-up of their preview at ARM TechCon. Dr. Joerg Winkler recently gave an updated webinar presentation of their approach in an implementation of ARM Cortex-A17 core.
By now, you’ve probably heard that 22FDX… Read More
I first met John Durbetaki at Intel in Aloha, Oregon and we both had a keen interest in the nascent personal computer industry. My first PC was made by Radio Shack and dubbed the TRS-80 which maxed out at 48KB of RAM. I kept watch on Durbetaki as he left Intel and formed his own company OrCAD in 1985 to serve the needs of PC-based CAD software.… Read More
One of the benefits of administering a leading semiconductor design enablement portal is that I get to see the traffic patterns then try and figure out what’s behind them. For example, a Cupertino domain has been reading all of our automotive content very thoroughly. We also get hits by Google.com, Amazon.com, and dozens of other… Read More
We tend to focus on connectivity and sensors for the IoT, however there is a third element to what I call the “Edge Device Triad” that is just as important: actuators. Making things move with microcontrollers (MCUs) is a science in and of itself. For small size and low weight combined with decent mechanical power, designers are opting… Read More
A trait shared by the fastest growing and most disruptive companies in history – Google, Amazon, Uber, AirBnb, and eBay – is that they aren’t focused on selling products, they are building platforms. The ability to leverage the network effects of a platform is something that the technology industry learned… Read More
For vision DSP IP running convolutional neural networks (CNNs), a big driver of performance is increasing the bits processed per cycle with parallel MACs. Tom Simon did a great job in recent posts of introducing CNNs at a high level, so I’ll look at what is architecturally behind Cadence’s latest announcement: the Tensilica Vision… Read More
The challenge of tracking design progress is a shared problem for individual designers, team leaders, and project managers. At each level the ability to step back from just reviewing error log files and seeing the arc of the whole design as it moves forward is valuable. The difficulty of seeing the whole picture is exacerbated when… Read More
If your team is building large, complex designs that require millions of clock cycles to fully verify, you need both simulation and emulation.
Using emulation with simulation accelerates performance for dramatically reduced run times.… Read More
I’ve been doing a lot of reading on silicon photonics lately and I’ve come to realize that while there is much written on the development of individual silicon photonic components and devices (modulators, photo detectors, optical amplifiers and such) that much of the cost and therefore chances of economic success… Read More
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Should Intel be Split in Half?