SILVACO 051525 Webinar 800x100 v2

SiFive execs share ideas on their RISC-V strategy

SiFive execs share ideas on their RISC-V strategy
by Don Dingee on 10-03-2016 at 4:00 pm

Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.


Previously, I covered… Read More


Microsoft, FPGAs and the Evolution of the Datacenter

Microsoft, FPGAs and the Evolution of the Datacenter
by Bernard Murphy on 10-03-2016 at 12:00 pm

When we think of datacenters, we think of serried ranks of high-performance servers. Recent announcements from Google (on the Tensor Processing Unit), Facebook and others have opened our eyes to the role that specialized hardware and/or GPUs can play in support of deep/machine learning and big data analytics. But most of us would… Read More


Could Machine Learning be Available for Mass Market?

Could Machine Learning be Available for Mass Market?
by Eric Esteve on 10-03-2016 at 7:00 am

Machine Learning is at the hype peak, according with Gartner’s August 2016 Hype Cycle for Emerging Technologies. The demand for vision processor IP is strong in smartphone, automotive and consumer electronics segments. ASSP based solutions can make the job, but how can OEM create differentiation, control their destiny and … Read More


Intel Altera FPGA at the heart of an autonomous Audi A8

Intel Altera FPGA at the heart of an autonomous Audi A8
by Claudio Avi Chami on 10-02-2016 at 4:00 pm

Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech. The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone Read More


100 Million Miles Per Hour!

100 Million Miles Per Hour!
by Kevin Kostiner on 10-02-2016 at 12:00 pm

Back When We Loved Discovery
As anyone who reads and follows my blog posts will know, I’m a believer in innovation. It’s what drives my passion for the Internet of Things. That interest started when I was an “Apollo” kid during the 1960’s and 1970’s. Those decades offered a very different landscape for creativity, exploration and… Read More


Scalable Infrastructure for Digital Businesses

Scalable Infrastructure for Digital Businesses
by Sudeep Kanjilal on 10-02-2016 at 7:00 am

Building Digital businesses is tough. The run-time changes rapidly (browser – apps – bots), and standards for the digital architecture/stack gets refined constantly. Pace of innovation is accelerating due to massive war-chest of the top digital players like Google, Facebook, Apple and Amazon. For the Fortune… Read More


Will TSMC be alone at 10nm and 7nm?!?!?

Will TSMC be alone at 10nm and 7nm?!?!?
by Daniel Nenni on 10-01-2016 at 7:00 am

Now that the dust has settled let’s talk about the recent TSMC OIP Ecosystem Forum. This was the 6[SUP]th[/SUP] annual OIP which hosts more than 1,000 attendees from TSMC’s top customers and partners. Presenting this year were TSMC VP and CTO Dr. Jack Sun, TSMC VP of R&D Dr. Cliff Hou, and ARM EVP of Incubation Businesses Dr. Dipesh… Read More


CCIX shows up in ARM CMN-600 interconnect

CCIX shows up in ARM CMN-600 interconnect
by Don Dingee on 09-30-2016 at 4:00 pm

All the hubbub about FPGA-accelerated servers prompts a big question about cache coherency. Performance gains from external acceleration hardware can be wiped out if the system CPU cluster is frequently taking hits from cache misses after data is worked on by an accelerator.

ARM’s latest third-generation CoreLink CMN-600 … Read More


Meet the POWER9 Chip Family

Meet the POWER9 Chip Family
by Alan Radding on 09-30-2016 at 12:00 pm

When you looked at a chip in the past you primarily were concerned with two things: the speed of the chip, usually expressed in GHz, and how much power it consumed. Today the IBM engineers preparing the newest POWER chip, the 14nm POWER9, are tweaking the chips for the different workloads it might run, such as cognitive or cloud, andRead More


Low power physical design in the age of FinFETs

Low power physical design in the age of FinFETs
by Beth Martin on 09-30-2016 at 7:00 am

Low power is now a goal for most digital circuit designs. This is to reduce costs for packaging, cooling, and electricity; to increase battery life; and to improve performance without overheating. I talked to the experts on physical design for ultra-low power at Mentor Graphics recently about the challenges to P&R tools and… Read More