Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read MoreeFabless and Silego $15,000 Go Configure Design Challenge Series!
The eFabless and Silego “Go Configure Design Challenge Series” is the first of its kind to allow a global community of designers to implement widely used functions using GreenPAK™ Configurable Mixed-signal ICs (“CMICs”) and its intuitive drag-and-drop software GUI. The efabless platform will serve as the crowd source design… Read More
Deal Struck for Sale of Toshiba NAND to Bain Apple and Others
What does it mean for the skyrocketing memory sector? In a last minute plot twist, Bain capital appears to be the winner in the auction of the Toshiba memory unit. The Bain consortium includes a strange cast of characters including Apple, Dell, Seagate, Kingston Technology, Innovation Network Corp of Japan and Development Bank… Read More
2017 Semiconductor Growth Approaching 20 Percent!
The 2017 semiconductor market is shaping up as the strongest since 2010 – when the market grew 32% as it bounced back from the 2008-2009 downturn. According to World Semiconductor Trades Statistics (WSTS), the second quarter 2017 semiconductor market was up 5.8% from 1Q 2017 and up 23.7% from a year ago. Much of the market vitality… Read More
GLOBALFOUNDRIES is Hitting on all Cylinders
On September 20th GLOBALFOUNDRIES (GF) held their annual technology conference. The conference presented an opportunity to hear the latest on the fascinating journey GF has been on.… Read More
What’s New with the I3C Standard
This month we’ve seen both Apple and Samsung announce their newest, flagship smart phones, and they each have an incredible number of sensors and components included like: … Read More
Design for Manufacturability Analysis for PCB’s
Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finer… Read More
Emulation Methodology for Drones and Other Video-Intensive Multimedia SoCs
What do drones, augmented reality devices, and 4K UHD TV have in common? They all include complex system-on-chips (SoCs) that must encode and decode, in real-time, data for increasingly higher definition video content. Verifying that these SoC designs are functionally correct is quite complex, but they must also function efficiently… Read More
High-Speed Equivalence Checking
Following on product introductions for simulation and prototyping, physical verification and implementation earlier in the year, Anirudh Devgan (Exec VP and GM at Cadence), the king of speed and parallelism has done it again, this time with logic equivalence checking (LEC). Cadence recently announced an advance to their well-known… Read More
Portable Stimulus Standard, What’s New from Cadence
I’ve been hearing about the Portable Stimulus Standard (PSS) since DAC 2016, so it’s helpful to get an update from EDA vendors on what their involvement level is with this emerging standard and how they see it helping design and verification engineers. Earlier in September I scheduled a conference call with Cadence… Read More


AI RTL Generation versus AI RTL Verification