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Semiconductor Expert Forum

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Safety qualification for leading edge IP elements – presentation at REUSE 2017 in Santa Clara

Safety qualification for leading edge IP elements – presentation at REUSE 2017 in Santa Clara
by Tom Simon on 12-06-2017 at 12:00 pm
Categories: Automotive, Events, IP, Silicon Creations

To ensure the reliability of automotive electronics, standards like AEC-Q100 and ISO 26262 have helped tremendously. They have created rational and explicit steps for developing and testing the electronic systems that go into our cars. These are not some abstract future requirement for fully autonomous cars, rather they are… Read More

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Enhancing FPGA Prototype Debug

Enhancing FPGA Prototype Debug
by Daniel Nenni on 12-06-2017 at 7:00 am
Categories: Prototyping, S2C EDA

FPGA prototyping is very popular in modeling hardware for early system prove-out, early embedded software development, as a cost-effective and performance-effective platform for software-driven hardware debug and for late-stage software debug, all before silicon is available. It has significant advantages in run-time… Read More

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Jump Start your Secure IoT Design with Intrinsix

Jump Start your Secure IoT Design with Intrinsix
by Mitch Heins on 12-05-2017 at 12:00 pm
Categories: Intrinsix, IoT, Semiconductor Services

Have you ever had a great idea for a new product but then stopped short of following through on it because of the complexities involved to implement it? It’s frustrating to say the least. It is especially frustrating, when the crux of your idea is simple, but complexity arises from required components that don’t add to the functionality… Read More

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Blurring Boundaries

Blurring Boundaries
by Bernard Murphy on 12-05-2017 at 7:00 am
Categories: Cadence, EDA, Prototyping

I think most of us have come to terms with the need for multiple verification platforms, from virtual prototyping, through static and formal verification, to simulation, emulation and FPGA-based prototyping. The verification problem space is simply too big, in size certainly but also in dynamic range, to be effectively addressed… Read More

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35 Semiconductor IP Companies Hold 2nd Annual Conference

35 Semiconductor IP Companies Hold 2nd Annual Conference
by Daniel Payne on 12-04-2017 at 12:00 pm
Categories: EDA, Events

Our smart phone driven semiconductor economy consumes a lot of IP blocks to enable quick product development cycles, often annually updating with new models to choose from. So where do you find all of the best semiconductor IP, verification IP and embedded software? Well, one place is at the 2nd annual REUSE conference, scheduled… Read More

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What are you ready to mobilize for FPGA debug?

What are you ready to mobilize for FPGA debug?
by Frederic Leens on 12-04-2017 at 7:00 am
Categories: EDA, FPGA

There are 3 common misconceptions about debugging FPGA with the real hardware:

[LIST=1]

  • Debugging happens because the engineers are incompetent.
  • FPGA debugging on hardware ‘wastes’ resources.
  • A single methodology should solve ALL the problems.
    • … Read More
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    RISC-V Business

    RISC-V Business
    by Tom Simon on 12-04-2017 at 7:00 am
    Categories: EDA, Events, RISC-V, SiFive

    I was at the 7[SUP]th[/SUP] RISC-V Workshop for two days this week. It was hosted by Western Digital at their headquarters in Milpitas. If you have not been following RISC-V, it is an open source Instruction Set Architecture (ISA) for processor design. The initiative started at Berkeley, and has been catching on like wildfire. … Read More

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    IP-SoC 2017: IP Innovation, Foundries, Low Power and Security

    IP-SoC 2017: IP Innovation, Foundries, Low Power and Security
    by Eric Esteve on 12-03-2017 at 12:00 pm
    Categories: Events, IP, IPnest, Semiconductor Services

    The 20[SUP]th[/SUP] IP-SoC conference will be held in Grenoble, France, on December 6-7, 2017. IP-SoC is not just a marketing fest, it’s the unique IP centric conference, with presentations reflecting the complete IP ecosystem: IP suppliers, foundries, industry trends and applications, with a focus on automotive. It will … Read More

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    Making Your Next Chip Self-Aware

    Making Your Next Chip Self-Aware
    by Daniel Payne on 12-01-2017 at 12:00 pm
    Categories: EDA, Events, Moortec
    4 Comments

    One holy grail of AI software developers is to create a system that is self-aware, or sentient. A less lofty goal than sentient AI is for chip designers to know how each specific chip responds to Process variations, Voltage levels and Temperature changes. If a design engineer knew exactly which process corner that each chip was fabricated… Read More

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    Hierarchy Applied to Semiconductor IP Reuse

    Hierarchy Applied to Semiconductor IP Reuse
    by Daniel Payne on 11-30-2017 at 12:00 pm
    Categories: EDA, Perforce

    When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More