Synopsys Announces Expanding AI Capabilities and EDA AI LeadershipIn the fast-paced semiconductor industry Synopsys has redefined…Read More
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)Introduction: The Historical Roots of Hardware-Assisted Verification The…Read More
Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
The Importance of Productizing AI. Everyday ExamplesKeeping up with the furious pace of AI…Read More
Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All… Read More
In the semiconductor world we have divided our engineering talent up into many adjacent disciplines and each comes with their own job titles: Design engineers, Verification engineers, DFT engineers, Test engineers. When first silicon becomes available then everyone on the team, and especially management all have a few big … Read More
Switching translates to power. Similar to the recent slow down experienced by Moore’s Law, the constant power density (power demand per unit chip area) prescribed by Dennard scaling was no longer affordable across the technological scaling. While the contribution of leakage power component in advanced process nodes was getting… Read More
I’m on a mini-roll on the subject of high-level design for ML-based systems. No complaints from me, this is one of my favorite domains and is certainly a hot area; it’s great to that EDA vendors are so active in advancing ML-based design. Here I want to talk about the Catapult HLS flow for use in ML design.
Since I’ve covered the ML topic… Read More
A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning… Read More
One of my favorite traditions at the Design Automation Conference is the Synopsys foundry events (the videos are now available). I learned a long time ago that the foundries are the foundation of the fabless semiconductor ecosystem and your relationships with the foundries can make or break you, absolutely. I also appreciate … Read More
Applied reported a more or less in line quarter, slightly beating weaker expectations. As we had projected, the October quarter is expected to have revenues down 10% which is at the low end of our expected 10-15% drop in business. Applied services helped partially make up for some of the equipment sales weakness. Revenue came in … Read More
Applied Materials (AMAT) is batting clean up in a quarter that has not been pretty. Lately semi stocks seem to have been hit by not only stock specific issues but continued and increasing memory concerns coupled with more macro issues. On top of all this, China trade issues which have in the meantime taken a back burner to other issues… Read More
The Linley Group is an industry-leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. Their Microprocessor Report is widely read as a source of un-biased, no-nonsense analysis of technologies and trends. So, when they dig into something… Read More
In high technology, there are numerous instances of highly productive groups coming together and generating game-changing ideas and products. This happened at Shockley Semiconductor in the 1960s when Gordon Moore, Bob Noyce, Jean Hoerni and… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet