Last year Arm announced their support for standards-based virtual prototyping in automotive, along with a portfolio of new AE (automotive enhanced) cores. They also suggested that in 2025 they would be following Arm directions in other LOBs by offering integrated compute subsystems (CSS). Now they have delivered: their Zena… Read More





High-NA Hard Sell: EUV Multi-patterning Practices Revealed, Depth of Focus Not Mentioned
In High-NA EUV lithography systems, the numerical aperture (NA) is expanded from 0.33 to 0.55. This change has been marketed as allowing multi-patterning on the 0.33 NA EUV systems to be avoided. Only very recently have specific examples of this been provided [1]. In fact, it can be shown that double patterning has been implemented… Read More
Anirudh Fireside Chats with Jensen and Lip-Bu at CadenceLIVE 2025
Anirudh (Cadence President and CEO) had two fireside chats during CadenceLIVE 2025, the first with Jensen Huang (Founder and CEO of NVIDIA) to kick off the show, and later in the day with Lip-Bu Tan (CEO of Intel). Of course Jensen and Lip-Bu also turn up for other big vendor shows but I was reminded that there is something special about… Read More
TCAD for 3D Silicon Simulation
Semiconductor fabs aim to have high yields and provide processes that attract design firms and win new design starts, but how does a fab deliver their process nodes in a timely manner without having to run lots of expensive silicon through the line? This is where simulation and TCAD tools come into play, and to learn more about this… Read More
Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination
Resistive RAM (ReRAM or RRAM) is the strongest candidate for next-generation non-volatile memory (NVM), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called ‘relaxation’ are making ReRAM more predictable — and easier to specify for real-world applications.… Read More
Breker Verification Systems at the 2025 Design Automation Conference #62DAC
Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio
Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.… Read More
The SemiWiki 62nd DAC Preview
After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More
CEO Interview with Kit Merker of Plainsight
Kit Merker is a technology industry leader with over 20 years of experience building software products. He serves as CEO of Plainsight Technologies and previously held senior positions at Nobl9, JFrog, Google and Microsoft.
Tell us about your company.
Plainsight is focused on making computer vision accessible and scalable … Read More
CEO Interview with Bjorn Kolbeck of Quobyte
Bjorn Kolbeck received a PhD in Computer Science from Humboldt University in Berlin. Bjorn had previously worked at HPC centers and at Google. His experience with hyperscale architectures led him to co-found Quobyte in 2013.
Tell us about your company?
Quobyte is scale-out storage, and was designed for massive scalability and… Read More
Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law
In this episode of the Semiconductor Insiders video series, Dan is joined by Dr Greg Law, CEO of Undo, He is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg explains the history of Undo, initially as a provider of software development and debugging tools for software vendors. He explains that… Read More
Intel Foundry is a Low Risk Aternative to TSMC