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Workflow Automation Applied to IP Lifecycle Management

Workflow Automation Applied to IP Lifecycle Management
by Daniel Payne on 10-04-2019 at 10:00 am

Methodics, Flowable

I often blog about a specific EDA tool, or an IP block, but the way that SoC design teams approach their designs and then use tools and IP can either be a manual, ad-hoc process, or part of something that is well-documented, following a design methodology. Back in the 1980’s while at Intel our team first created a design methodology… Read More


The GF Pivot, Specialization Defined

The GF Pivot, Specialization Defined
by Randy Smith on 10-04-2019 at 6:00 am

On August 27, 2018, GLOBALFOUNDRIES (GF) announced that they were no longer going to compete in the race to the next smaller semiconductor node, at that time, the 7nm node. While surprising to some, on further analysis this move made sense. TSMC had announced its plan to invest around $25B in the 5nm technology node. GF revenue is … Read More


Synopsys and Infineon prepare for expanding AI use in automotive applications

Synopsys and Infineon prepare for expanding AI use in automotive applications
by Tom Simon on 10-03-2019 at 10:38 am

We all know that cars are using processors for many tasks, but it is easy to fail to comprehend just how many there are in a typical modern car. Browsing through the Infineon AURIX automotive processor application guide, you can start to see just how pervasive processors are. The AURIX processors are specifically designed for automotive… Read More


AI Hardware Summit, Report #3: Enabling On-Device Intelligence

AI Hardware Summit, Report #3: Enabling On-Device Intelligence
by Randy Smith on 10-03-2019 at 6:00 am

This is the third and final blog I have written about the recent AI Hardware Summit held at the Computer History Museum in Mountain View, CA. Day 1 of the conference was more about solutions in the data center, whereas Day 2 was primarily around solutions at the Edge. This presentation from Day 2 was given by Dr. Thomas Anderson, Head,… Read More


Debugging SoCs at the RTL, Gate and SPICE Netlist Levels

Debugging SoCs at the RTL, Gate and SPICE Netlist Levels
by Daniel Payne on 10-02-2019 at 10:00 am

Concept Engineering - auto schematic

Debugging an IC is never much fun because of all the file formats used, the levels of hierarchy and just the sheer design size, so when an EDA tool comes around that allows me to get my debugging done quicker, then I take notice and give it a look. I was already familiar with debugging SPICE netlists using a tool called SPICEVision Pro,… Read More


Acceleration in a Heterogenous Compute Environment

Acceleration in a Heterogenous Compute Environment
by Bernard Murphy on 10-02-2019 at 5:00 am

Acceleration

Heterogenous compute isn’t a new concept. We’ve had it in phones and datacenters for quite a while – CPUs complemented by GPUs, DSPs and perhaps other specialized processors. But each of these compute engines has a very specific role, each driven by its own software (or training in the case of AI accelerators). You write software… Read More


Webinar: OCV and Timing Closure Sign-off by Silvaco on Oct 10 at 10AM

Webinar: OCV and Timing Closure Sign-off by Silvaco on Oct 10 at 10AM
by Daniel Nenni on 10-01-2019 at 10:00 am

The old adage that goes the one constant thing you can always count on is change, could easily be reworded for semiconductor design to say the one constant thing you can count on is variation. This is doubly true. Not only is variation, in all its forms, a constant factor in design, additionally the methods of analyzing and dealing … Read More


Webinar: Finding Your Way Through Formal Verification

Webinar: Finding Your Way Through Formal Verification
by Bernard Murphy on 10-01-2019 at 6:00 am

Finding your way through formal book

Formal verification has always appeared daunting to me and I suspect to many other people also. Logic simulation feels like a “roll your sleeves up and get the job done” kind of verification, easily understood, accessible to everyone, little specialized training required. Formal methods for many years remained the domain of … Read More


AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS
by Randy Smith on 09-30-2019 at 10:00 am

I previously wrote a blog about a session from Day 1 of the AI Hardware Summit at the Computer History Museum in Mountain View, CA, held just last week. From Day 2, I want to delve into this presentation by Bryan Bowyer, Director of Engineering, Digital Design & Implementation Solutions Division at Mentor, a Siemens Business.… Read More


Crashing the Mars Rovers!!! Actel and Aerospace Corp

Crashing the Mars Rovers!!! Actel and Aerospace Corp
by John East on 09-30-2019 at 6:00 am

In early 2003 Actel announced a new product family:  RTSX-A.  It was a family of antifuse FPGAs aimed at the satellite market.  Customers had known for a long time that it was coming and there had been prototypes available for many months.  Our space customers loved the product.  This was going to be a big win for us!  One of the first… Read More