TSMC's new 3nm project reportedly halted; industry insiders reveal underlying reasons and strategic considerations

[Daniel Nenni]

Industry insiders point out that TSMC's move also carries strategic considerations, aiming to guide customers to shift their new product planning towards the 2-nanometer advanced process. (Photo/Associated Press)

• [Chang Chia-jui/Las Vegas Report] TSMC, the world's leading semiconductor foundry, is maintaining high capacity utilization for its advanced processes, with its 3nm process continuing to face supply shortages. Chip industry insiders revealed that in addition to raising its 3nm prices this year, TSMC has temporarily halted the kick-off of new 3nm projects. Semiconductor analysts attribute this primarily to fully booked orders, existing capacity being insufficient to meet demand, and the inability to expand production in the short term to keep pace with the surge in customer demand.
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• Industry insiders further pointed out that TSMC's move also carries strategic considerations, aiming to guide customers to shift their new product planning towards the 2nm advanced process. Because 2nm offers a better cost structure, and with the support of key technologies such as atomic layer deposition (ALD), the number of extreme ultraviolet (EUV) exposure layers has not increased significantly. The value of the process is shifting to the materials side, bringing to the forefront supply chain players such as Chung-Shan Semiconductor, Suntech Power Systems, and U-Chuan Materials.

TSMC's 3nm family includes multiple versions, but its current production capacity is fully booked by customers for AI GPUs, cloud data center ASICs, and high-end mobile processors.

Due to the difficulty in keeping up with the surge in orders in the short term, TSMC has chosen to postpone the development of new 3nm projects. Chip industry insiders further pointed out that TSMC is encouraging customers who are still in the early stages of product planning to directly evaluate the adoption of 2nm process technology to facilitate subsequent mass production and cost configuration.

TSMC's 2nm process has entered mass production, with Apple, Qualcomm, and MediaTek being its main customers for mobile phone chips. Chip industry insiders revealed that the actual price of 2nm chips is not as high as the outside world thought, exceeding US$30,000 per chip, but it is indeed a "noticeable" increase compared to N3P prices. However, through the combination of large and small chips and the large shipment volume to amortize costs, the processor SoC is not the main reason for the surge in smartphone BOM (Bill of Materials) costs compared to memory chips.

Industry analysts believe that 2nm is a significant turning point for TSMC's advanced processes. It not only introduces nanosheet transistor architecture for the first time, offering clear advantages in performance, power consumption, and density, but also demonstrates a better cost structure in process design. Compared to 3nm, 2nm, while incorporating advanced processes such as atomic layer deposition (ALD), does not significantly increase the number of EUV exposure layers, making the overall manufacturing cost per chip more competitive. This has become a key factor for TSMC in actively encouraging customers to switch to 2nm.

Semiconductor industry insiders revealed that the GAAFET process upgrades wafer manufacturing from planar engraving to three-dimensional construction, increasing the process difficulty exponentially. It must overcome key challenges such as silicon/germanium alternating stacked epitaxial growth, high aspect ratio etching, and atomic-level ALD gate coating. Among these challenges, the ALD needs to form a uniform, defect-free high-dielectric layer and metal gate around the suspended structure, which places near-limit requirements on deposition consistency.

https://www.ctee.com.tw/news/20260108700068-430501

 

[Daniel Nenni]

CC Wei is one of the smartest business men you will meet in the semiconductor industry, absolutely. TSMC N3 is a great example. TSMC is the only option at 3nm but there was no way to know that for sure since Intel and Samsung were making a lot of competitive noise. It turned out to be nonsense thus TSMC owns 99% of the 3nm business. A similar thing happened at 28nm. TSMC competitors made lots of competitive noise but didn't yield so TSMC owned the node and was on allocation.

TSMC N3 is not on allocation but capacity is tight which makes everyone nervous except CC Wei because that is how you run a foundry. Utilization should always be high and capacity tight. That is why TSMC stock is so high compared to when Morris Chang was CEO. TSM was in the $30s when CC Wei took over in June of 2018 and is now in the $300s. That is the power of CC Wei.

Pricing is also making people nervous. Wafer price negotiation is a standard industry practice but how do you negotiate 3nm wafers when TSMC is the only source? And even if you have other foundry options you will not have pricing leverage unless you actually use those options. This is why TSMC will put a lot of focus on N2 since Intel 18A, Samsung 2nm, and Rapidus 2nm are making competitive noise.

This is what I call the NOT TSMC market. Customers will use Intel 18A, Samsung 2nm and Rapidus 2nm to get better pricing from TSMC but probably not on big projects. I can see Apple using Intel 18A for the M series SOCs. I have a new M5 series iPad Pro and it is amazing. Microsoft, Amazon, Qualcomm, Marvell, MediaTek, and Broadcom can also use Intel 18A, Samsung 2nm and Rapidus 2nm. I do not see Nvidia or AMD using other fabs since the CEOs are very close friends and compatriots. Everyone else is up for grabs, my opinion.

 

[Xebec]

The 10X stock price runup in 7.5 years is excellent. Historical stock market trends would suggest only 2X over that time. In 2018, though the winds were blowing in TSMC's favor, their runaway success wasn't a foregone conclusion. (I wish I had invested, though my "risk tolerant" funds went to TSLA in 2018 instead.. )

I assume your comments on negotiating with TSMC is rhetorical But I think the total silicon TAM decreases as the price of a wafer goes up as a wafer becomes too expensive for a given customer use case. (Is Intel the only TSMC customer left with any real negotiating power? ). I would also think Nvidia might dabble with Intel fabs given it's cash infusion to Intel?

Of course in this market with LLM-mania, the sky is the limit for TSMC..

 

[IanD]

From what we've seen the wafer cost increase with N2 is bigger than the die area saving compared to N3, so for the same function an N2 chip is more expensive than N3 -- but of course also has lower power consumption for the same speed or higher speed for the same power, which is the real reason for using it not cost.

Given the quotes about number of EUV exposures and use of ALD it's possible that this gap will close or maybe eventually reverse (so N2 is cheaper) as the process matures, but that's likely to be at least a couple of years away.

There are also some pretty significant speed/power advantages with N2 for ultra-high-speed circuits like SERDES/transcievers because GAA has much lower gate access resistance than FinFET, but this doesn't affect the vast majority of CMOS circuits.

 

[siliconbruh999]

From what we've seen the wafer cost increase with N2 is bigger than the die area saving compared to N3, so for the same function an N2 chip is more expensive than N3 -- but of course also has lower power consumption for the same speed or higher speed for the same power, which is the real reason for using it not cost.

Given the quotes about number of EUV exposures and use of ALD it's possible that this gap will close or maybe eventually reverse (so N2 is cheaper) as the process matures, but that's likely to be at least a couple of years away.

There are also some pretty significant speed/power advantages with N2 for ultra-high-speed circuits like SERDES/transcievers because GAA has much lower gate access resistance than FinFET, but this doesn't affect the vast majority of CMOS circuits.

Do you have any Idea with regards to18A or SF2 vs how they stack vs N2

 

[IanD]

Do you have any Idea with regards to18A or SF2 vs how they stack vs N2

No, only TSMC -- my comments are based on actual designs not speculation, and we don't use Intel or Samsung...