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Driving Data Frontiers: High-Performance PCIe® and CXL® in Modern Infrastructures

Driving Data Frontiers: High-Performance PCIe® and CXL® in Modern Infrastructures
by Kalar Rajendiran on 06-10-2024 at 10:00 am

Alphawave Ecosystem Collaborative Partners

The increasing demands of data-intensive applications necessitate more efficient storage and memory utilization. The rapid evolution of AI workloads, particularly with Generative AI (GenAI), demands infrastructure that can adapt to diverse computational needs. AI models vary widely in resource requirements, necessitating… Read More


TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design

TSMC Advanced Packaging Overcomes the Complexities of Multi-Die Design
by Mike Gianfagna on 06-10-2024 at 6:00 am

TSMC Advanced Packaging Overcomes the Complexities of Multi Die Design

The TSMC Technology Symposium provides a worldwide stage for TSMC to showcase its advanced technology impact and the extensive ecosystem that is part of the company’s vast reach. These events occur around the world and the schedule is winding down. TSMC covers many topics at its Technology Symposium, including industry-leading… Read More


Blank Wafer Suppliers are not Totally Blank

Blank Wafer Suppliers are not Totally Blank
by Claus Aasholm on 06-09-2024 at 8:00 am

Sand to Semiconductors

AI requires more Silicon capacity
Deep in the supply chain, some wizards turn sand into perfect diamond-structured crystal disks of silicon, which are necessary for the entire semiconductor supply chain.

They are part of the semiconductor supply chain, making Silicon Sand almost a thousand times more valuable.

The glimmer … Read More


Podcast EP227: The Significance of the RISC-V Movement and the Upcoming Andes RISC-V event with Mark Himelstein

Podcast EP227: The Significance of the RISC-V Movement and the Upcoming Andes RISC-V event with Mark Himelstein
by Daniel Nenni on 06-07-2024 at 10:00 am

Dan is joined by Mark Himelstein, President of Heavenstone. Most recently, as Chief Technology Officer at RISC-V International, Mark contributed to shaping RISC-V technology through visionary leadership and industry expertise. He has a track record of executive roles at Graphite Systems, Quantum, and Infoblox.

Dan discusses… Read More


Accelerate SoC Design: Addressing Modern Prototyping Challenges with S2C’s Comprehensive Solutions (II)

Accelerate SoC Design: Addressing Modern Prototyping Challenges with S2C’s Comprehensive Solutions (II)
by Daniel Nenni on 06-07-2024 at 8:00 am

Prodigy

In the fast-paced world of Electronic Design Automation (EDA), the complexity of chip designs is continuously rising. With the burgeoning of systems such as 5G communication devices and Advanced Driver-Assistance Systems (ADAS) teeming with thousands of components, the demand for robust and efficient prototyping platforms… Read More


CEO Interview: Dieter Therssen of Sigasi

CEO Interview: Dieter Therssen of Sigasi
by Daniel Nenni on 06-07-2024 at 6:00 am

Dieter Therssen

Dieter Therssen obtained his master’s degree in Electronics Engineering from KU Leuven in 1987. He started his career as a hardware design engineer, using IMEC’s visionary tools and design methodologies in the early days of silicon integration.

Since then, Dieter developed his career across many digital technologies,… Read More


3DIC Verification Methodologies for Advanced Semiconductor ICs

3DIC Verification Methodologies for Advanced Semiconductor ICs
by Kalar Rajendiran on 06-06-2024 at 10:00 am

3DIC Flow Challenges

At the recent User2user conference, Amit Kumar, Principal Hardware Engineer, Microsoft, shared the company’s experience from building a 3DIC SoC and highlighted Siemens EDA tools that were used. The following is a synthesis of core aspects of that talk.

3DIC Challenges

Despite the numerous advantages of 3DIC technology, its… Read More


Mastering Copper TSV Fill Part 3 of 3

Mastering Copper TSV Fill Part 3 of 3
by John Ghekiere on 06-06-2024 at 8:00 am

Mastering Copper TSV Fill Part 3 of 3

Establishing void-free fill of high aspect ratio TSVs, capped by a thin and uniform bulk layer optimized for removal by CMP, means fully optimizing each of a series of critical phases. As we will see in this 3-part series, the conditions governing outcomes for each phase vary greatly, and the complexity of interacting factors means… Read More


Arteris is Solving SoC Integration Challenges

Arteris is Solving SoC Integration Challenges
by Mike Gianfagna on 06-06-2024 at 6:00 am

Arteris is Solving SoC Integration Challenges

The difficulty of SoC integration is clearly getting more demanding. Driven by process node density, multi-chip integration and seemingly never-ending demands for more performance at lower power, the hurdles continue to increase. When you consider these challenges in the context of Arteris, it’s natural to think about hardware… Read More


What to Do with All that Data – AI-driven Analysis Can Help

What to Do with All that Data – AI-driven Analysis Can Help
by Rob vanBlommestein on 06-05-2024 at 10:00 am

1 design da

Today’s advanced node chip designs are faced with many new complexities from design and verification down to manufacturing. The solutions used at every stage of chip development generate petabytes of data. Managing, analyzing, understanding, and acting upon that data is overwhelming and paralyzing. Manual interpretation… Read More