Bloomberg did an interview with my favorite semiconductor analyst Stacy Rasgon on “How the Number One U.S. Semiconductor Company Stumbled” that I found interesting. Coupled with the Q&A Bob Swan did at the Credit Suisse Annual Technology Conference I thought it would be good content for a viral blog.





Quantum Internet Explained
Building a quantum internet is a key ambition for many countries around the world, such a breakthrough will give them competitive advantage in a promising disruptive technology, and opens a new world of innovations and unlimited possibilities.
Recently the US Department of Energy (DoE) published the first blueprint of its… Read More
The Future of Connected Car Advertising
“Ads definitely work, but we can’t tell you how or why or give you any evidence,” – Tim Hwang, research fellow, Georgetown Center for Security and Emerging Technology
Two recent episodes of the Freakonomics Radio podcast tackle the question “Does advertising actually work?” and they coincided with a presentation… Read More
CEO Interview: Tony Pialis of Alphawave IP
Tony Pialis is a visionary entrepreneur focused on developing
technologies for next generation connectivity. In the last twenty 20 years, he has co-founded three semiconductor IP companies, all exclusively targeting connectivity IP. Tony is currently the CEO of Alphawave IP Inc, a leader in delivering multi-standard wireline… Read More
Chip Startups are Succeeding with Silicon Catalyst and Partners Like Arm
Earlier this year I wrote about Silicon Catalyst and a potent new addition to their In-Kind and Strategic Partner Programs, Arm. Fast-forward to today and there are real results to report. As I mentioned in the prior post, Silicon Catalyst provides a unique incubator environment which includes deeply discounted technology … Read More
Curvilinear FPD Layout and Schematics
You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:
What follows is the second part of a Q&A discussion with Chen Zhao… Read More
Sign Off Design Challenges at Cutting Edge Technologies
As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More
Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
The industry recently concluded a series of technology events for the all the major foundries. Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More
No Intel and Samsung are not passing TSMC
Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More
A Fast Checking Methodology for Power/Ground Shorts
The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow. The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet