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The Semiconductor Industry Has High Hopes That Biden Will Change Tracks

The Semiconductor Industry Has High Hopes That Biden Will Change Tracks
by Terry Daly on 12-13-2020 at 8:00 am

US China Semiconductor Biden

What is the “right track” for US-China trade relations?

The semiconductor industry has been squarely in the crosshairs of US-China trade tensions for four years. As the US faces a presidential leadership transition, will a Biden administration change the dynamic? The chip industry is counting on it, and China hopes so too.

In … Read More


Tesla: The Eyes Have It

Tesla: The Eyes Have It
by Roger C. Lanctot on 12-13-2020 at 6:00 am

Tesla The Eyes Have It

David Zipper of Harvard’s Kennedy School writes in Slate that the incoming Biden Administration should “bring the hammer down” on Tesla Motors for its mis-labeled and therefore misleading Autopilot application and the recently updated Full Self-Driving software beta in the interest of the general public. Zipper’s plan,

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HFSS Performance for “Almost Free”

HFSS Performance for “Almost Free”
by Jim DeLap on 12-11-2020 at 10:00 am

HFSS PCB

Everyday, engineers are running simulations to deliver the next generation of products to make our lives better. Everyday, they wait for those simulations to finish, wishing that they could get answers instantaneously. While waiting for those simulations or checking on the status of their runs at night, they might indulge in… Read More


Configuration Environment is Make-or-Break for IC Verification

Configuration Environment is Make-or-Break for IC Verification
by Tom Simon on 12-10-2020 at 10:00 am

IC Verification Environment

All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical… Read More


IEDM 2020 Starts this Weekend

IEDM 2020 Starts this Weekend
by Scotten Jones on 12-10-2020 at 6:00 am

IEDM 2020 Logo

As I have discussed before, I believe that IEDM is the premier technical conference for understanding leading edge process technologies. Beginning this coming weekend, this year’s edition of IEDM will be held virtually, and I highly recommend attending.

The conference held a press briefing last Monday. The tutorial and short… Read More


Altair Expands Its Technology Footprint with I/O Profiling from Ellexus

Altair Expands Its Technology Footprint with I/O Profiling from Ellexus
by Mike Gianfagna on 12-09-2020 at 10:00 am

Altair Expands Its Technology Footprint with IO Profiling from Ellexus

Altair is a broad-based technology company with an ambitious vision. As stated on their website: Our comprehensive, open-architecture solutions for data analytics, computer-aided engineering, and high-performance computing (HPC), enable design and optimization for high performance, innovative, and sustainable productsRead More


Smoother MATLAB to HLS Flow

Smoother MATLAB to HLS Flow
by Bernard Murphy on 12-09-2020 at 6:00 am

A better design path from MATLAB 1 min

It hard to imagine design of a complex signal processing or computer vision application starting somewhere other than in MATLAB. Prove out the algorithm in MATLAB, then re-model in Simulink, to move closer to hardware. First probably an architectural model, using MATLAB library functions to prove out behavior of the larger system.… Read More


How Line Cuts Became Necessarily Separate Steps in Lithography

How Line Cuts Became Necessarily Separate Steps in Lithography
by Fred Chen on 12-08-2020 at 10:00 am

How Line Cuts Became Necessarily Separate Steps in Lithography

Pretty much all the semiconductor nodes in the last two decades have had at least one layer where the minimum pitch pushes the limitation of the state-of-the-art lithography tool, with a k1 factor < 0.5, i.e., the half-pitch is less than 0.5*wavelength/numerical aperture. A number of published reports [1-4] have touched upon… Read More


Verification IP proves essential for PCIe GEN5

Verification IP proves essential for PCIe GEN5
by Tom Simon on 12-08-2020 at 6:00 am

PCIe Verification IP

PCI Express (PCIe) has become an important communication element in a wide range of systems. It is used to connect networking, storage, FPGA and GPGPU boards to servers and desktop systems. It has progressed a long way from its initial parallel bus format. Its evolution to a serial point to point configuration has been accompanied… Read More


The Practitioners View of DAC – Design, IP and Embedded

The Practitioners View of DAC – Design, IP and Embedded
by Mike Gianfagna on 12-07-2020 at 10:00 am

The First DAC

Next year will mark the 58th year for the Design Automation Conference. It’s hard to wrap your head around the fact this event dates back to 1964, when rock ‘n roll was new, cars were big and computers were even bigger. In its early days, the event was called the Design Automation Workshop. Pictured above is the cover of the very first… Read More