I can remember back in the 1980s how Apollo workstations were quite popular, because they accelerated the graphics display time for EDA tools much better than competitive hardware. Fast forward to 2022 and we have the same promise of speeding up EDA tools like PCB layout editing by using a GPU. At the 58th DAC there was a session called,… Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read MoreWEBINAR: Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
Among the multiple technologies that are poised to deliver substantial value in the future, Artificial Intelligence (AI) tops the list. An IEEE survey showed that AI will drive the majority of innovation across almost every industry sector in the next one to five years.
As a result, the AI revolution is motivating the need for … Read More
An Ah-Ha Moment for Testbench Assembly
Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing their energy in learning UVM. UVM is fine, so why do we need to talk about anything different? That’s the forest and trees thing. We don’t … Read More
Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
The much anticipated (virtual) DVCON 2022 is happening this week and functional verification plus UVM is a very hot topic. Functional Verification Engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep… Read More
Intel’s Investor Day – Nothing New
Intel’s big investor day was anything but big. The stock reacted poorly, down 5% on a day that was a widespread sell-off anyways.
I want to briefly summarize what matters for the stock. There was very little incremental news to the technology roadmap, and the financial outlook was underwhelming, to say the least.
The revenue guide… Read More
Podcast EP64: The real story behind Fairchild Semiconductor
Dan is joined by John East, the former CEO of Actel. In the sixth episode of Semiconductor Insiders John explained the beginnings of Fairchild Semiconductor and the significance of the Traitorous Eight.
In this follow-up discussion, John recounts the rise and fall of Fairchild Semiconductor. This is a turbulent and significant … Read More
CEO Interview: Tamas Olaszi of Jade Design Automation
Why does the industry need another register management tool? This is a question that Tamas Olaszi, the founder of Jade Design Automation hears from time to time since Jade-DA brought Register Manager, their EDA tool, to market. So why?
There is a genuine answer to this question but first let me use this interview to give some helpful… Read More
Integrated 2D NoC vs a Soft Implemented 2D NoC
We are living in the age of big data and the future is going to be even more data centric. Today’s major market drivers all have one thing in common: efficient management of data. Whether it is 5G, hyperscale computing, artificial intelligence, autonomous vehicles, or IoT, there is data creation, processing, transmission, and … Read More
Scalable Verification Solutions at Siemens EDA
Lauro Rizzatti recently interviewed Andy Meier, product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr.… Read More
Working with the Unified Power Format
The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More


I Have Seen the Future with ChipAgents Autonomous Root Cause Analysis