As multi-die and chiplet-based system designs become more prevalent in advanced electronics, much of the focus has been on physical design challenges. However, verification—particularly functional correctness and interoperability of inter-die connections—is just as critical. Interfaces such as UCIe or custom interconnects… Read More



S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying… Read More
A Quick Tour Through Prompt Engineering as it Might Apply to Debug
The immediate appeal of large language models (LLMs) is that you can ask any question using natural language in the same way you would ask an expert, and it will provide an answer. Unfortunately, that answer may be useful only in simple cases. When posing a question we often implicitly assume significant context and skate over ambiguities.… Read More
Chiplets and Cadence at #62DAC
Using chiplets is an emerging trend well-covered at #62DAC and they even had a dedicated Chiplet Pavilion, so I checked out the presentation from Dan Slocombe, Design Engineering Architect in the Compute Solutions Group at Cadence. In a short 20 minutes Dan managed to cover a lot of ground, so this blog will summarize the key points.… Read More
What XiangShan Got Right—And What It Didn’t Dare Try
An Open ISA, a Closed Mindset — Predictive Execution Charts a New Path
The RISC-V revolution was never just about open instruction sets. It was a rare opportunity to break free from the legacy assumptions embedded in every generation of CPU design. For decades, architectural decisions have been constrained by proprietary patents,… Read More
The Critical Role of Pre-Silicon Security Verification with Secure-IC’s Laboryzr™ Platform
As embedded systems and System-on-Chip (SoC) designs grow in complexity and integration, the risk of physical attacks has dramatically increased. Modern day adversaries no longer rely solely on software vulnerabilities; instead, they exploit the physical properties of silicon to gain access to sensitive data. Side-channel… Read More
Should Intel be Split in Half?
A recent commentary from four former Intel board members argue that Intel should be split into two separate companies with separate CEOs and separate board of directors. Charlene Barshefsky, Reed Hundt, James Plummer, and David Yoffie wrote that Intel shareholders should insist on a split which would create a new, independent,… Read More
CEO Interview with Karim Beguir of InstaDeep
Karim Beguir is InstaDeep’s Chief Executive Officer. He helps companies get to grips with the latest AI breakthroughs and deploy these in order to improve efficiency and ROI. As a graduate of France’s Ecole Polytechnique and former Program Fellow at NYU’s Courant Institute, Karim has a passion for teaching and using… Read More
Podcast EP302: How MathWorks Tools Are Used in Semiconductor and IP Design with Cristian Macario
Dan is joined by Cristian Macario, senior technical professional at MathWorks, where he leads global strategy for the semiconductor segment. With a background in electronics engineering and over 15 years of experience spanning semiconductor design, verification, and strategic marketing, Cristian bridges engineering … Read More
Making Intel Great Again!
Lip-Bu Tan made it very clear on his most recent call that Intel will not continue to invest in leading edge semiconductor manufacturing solo. Lip-Bu is intimately familiar with TSMC and that is the collaborative business model he envisions for Intel Foundry. I support this 100%. Intel and Samsung have tried to compete head-to-head… Read More
A Quick Tour Through Prompt Engineering as it Might Apply to Debug