Technical Case Study: MicroLED Yield Management with Plessey and yieldWerxPlessey Semiconductors manufactures monolithic MicroLED displays for near-eye…Read More
Unified Emulation and Prototyping: Pipedream or Reality?Preamble Hardware-assisted verification (HAV) platforms, including hardware emulators…Read More
HBM’s Vertical Ascent: Why Packaging Is Becoming the Heart of AI MemorySK hynix’s Hot Chips 2026 presentation explains how…Read More
Containing AI Agents With a Will of Their OwnMeta recently open-sourced a capable, large-scale agent model…Read More
Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First GenerationIntel Foundry has a blog on LinkedIn that is…Read More
On Friday April 12th Intel held a press briefing on their adoption of High NA EUV with Intel fellow and director of lithography Mark Phillips.
In 1976 Intel built Fab 4 in Oregon, the first Intel fab outside of California. With the introduction of 300mm Oregon became the only development site for Intel with large manufacturing, development,… Read More
Unit shipments of both PCs and smartphones versus a year ago have turned positive. According to IDC, PC shipments in 1Q 2024 were up 1.5% from 1Q 2023, the first positive year-to-year change since 4Q 2021. Smartphone year-to-year growth turned positive in 4Q 2023 at 8.5%. The growth continued in 1Q 2024 at 7.8%. 4Q 2023 was the first… Read More
Ben Packman, Senior Vice President at PQShield, leads global expansion through sales and partner growth across multiple vertical markets, alongside taking a lead role in briefing both government and the supply chain on the quantum threat.
Tell us a little bit about yourself and your company.
PQShield is a post-quantum cryptography… Read More
“Real men have fabs” was an insult AMD founder Jerry Sanders hurled at his poor competitors who could not afford to build fabs. A few years later, AMD would be fabless, spinning off its manufacturing facilities as GlobalFoundries. This was the beginning of a transformative period for the industry.
Lisa Su could rightfully retort:
How much can running on a multi-core (Arm) CPU speed up fault simulation? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
There has been much interest in Huawei’s and SMIC’s plans for 5nm production in the near future. Since there is no use of EUV in China, immersion DUV lithography (with a 76 nm pitch resolution) is expected to be used along with pitch quartering to achieve pitches in the 20-30 nm range expected for the 5nm and 3nm nodes [1].… Read More
Securing the data and all the associated transactions that comprise our hyper-connected world is a daunting task. Security touches the hardware, software and all the channels connecting every device and every transaction. Threats can be embedded in software, hardware or systems can be compromised externally using a large … Read More
TechInsights recognizes Earth Day 2024 by lifting the screen on smartphone semiconductor sustainability
Smartphones are typically compared based on screen size, processor speed, and camera resolution. But when TechInsights looked at carbon footprints for manufacturing just the semiconductors of three flagship phones,… Read More
Synopsys recently hosted an information rich-webinar, modestly titled “Improving Quality, FuSa, Reliability, and Security in Automotive Semiconductors”. I think they undersold the event; this was really about managing all of those things through the lifecycle of a car, in line with auto OEMs strategies for the future of the… Read More
Dan is joined by Robert Ruiz, product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas… Read More
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The $9.5 Billion Design IP Market: Shifting Boundaries, Arm’s Monopoly, and the RISC-V Response