No doubt that the design success of nowadays system on chips (SoCs) is directly linked to the success of cost control. More market opportunities are open for less expensive system on chips and electronic systems.
Both the design cost prediction and the resource tracking during the design process, are key to such a success
Predicting… Read More
Dan is joined by Dr. Raj Jammy of MITRE Engenuity. As Chief Technologist, Raj is responsible for incubating and accelerating technologies in partnership with the private sector, and for developing strategic frameworks that promote technologies for the public good. A seasoned semiconductor/electronics industry executive,… Read More
With AI applications proliferating, many designers are looking for ways to reduce server footprints in data centers – and turning to FPGA-based accelerator cards for the job. In a 20-minute session, Salvador Alvarez, Sr. Manager of Product Planning at Achronix, provides insight on the potential of FPGAs for real-time machine… Read More
Ansys is hosting IDEAS Digital Forum 2022, a no-cost virtual event that brings together industry executives and technical design experts to discuss the latest in EDA for Semiconductors, Electronics, and Photonics.
See the full online conference agenda and list of speakers at www.ansys.com/IDEAS. The free registration will… Read More
Over the last couple of decades, the electronics communications industry has been a significant driver behind the growth of the FPGA market and continues on. A major reason behind this is the many different high-speed interfaces built into FPGAs to support a variety of communications standards/protocols. The underlying input-output… Read More
The Role of Clock Gatingby Steve Hoover on 11-28-2022 at 10:00 amCategories: EDA
Perhaps you’ve heard the term “clock gating” and you’re wondering how it works, or maybe you know what clock gating is and you’re wondering how to best implement it. Either way, this post is for you.
Why Power Matters
I can’t help but laugh when I watch a movie where the main characters are shrunk… Read More
Looking for better ways to search a huge state space in model checking, Ant Colony Optimization (ACO) is one possible approach. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More
A Crash Course in the Future of Technologyby Vivek Wadhwa on 11-27-2022 at 2:00 pmCategories: Cadence, EDA
One of the harshest lessons we learned during the recent pandemic is the power of exponentials. As human beings, we are linear thinkers and can’t fathom how doublings of viruses — or technologies — can be destructive and disrupt everything. In my university classes and talks to business executives, I have always had to explain… Read More
Dan is joined by Dr. Suresh Venkatesan, chairman and CEO, POET Technologies. Suresh joined POET Technologies from GLOBALFOUNDRIES where he served as senior vice president, Technology Development. He is an industry veteran with over 22 years of experience in semiconductor technology development. Prior to joining GLOBALFOUNDRIES,… Read More
On November 10th I watched the presentation by L.C. Lu, TSMC Fellow & VP, as he talked about enabling system innovation with dozens of slides in just 26 minutes. TSMC is the number one semiconductor foundry in the world, and their Open Innovation Platform (OIP) events are popular and well attended as the process technology and… Read More
Intel’s Pearl Harbor Moment