In verification there is an ever-popular question, “When can we stop verifying?” The intent behind the question is “when will we have found all the important bugs?” but the reality is that you stop verifying when you run out of time. Any unresolved bugs appear in errata lists delivered with the product (some running to 100 or more … Read More


Podcast EP156: A Chat With Shankar Krishnamoorthy About Strategy and Outlook for EDA Development at SNUG
This is another special edition of our podcast series. SemiWiki staff writer Kalar Rajendiran spoke with Shankar Krishnamoorthy, General Manager, Electronic Design Automation Group for Synopsys at the recent SNUG meeting,
Shankar discusses how Synopsys is focusing on hyperconvergence and implementation of AI across the… Read More
ASML Wavering- Supports our Concern of Second Leg Down for Semis- False Bottom
-ASML weakness is evidence of deeper chip down cycle
-When ASML sneezes other chip equip makers catch a cold
-Will backlog last long enough? Will EUV demand hold up?
-“Unthinkable” event, litho cancelations, could shock industry
ASML has in line quarter but alarm bells ring on wavering outlook
ASML reported Euro6.7B… Read More
Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!
Design IP revenues had achieved $6.67B in 2022, after $5.56B in 2021, or 20.2% growth after 19.4% in 2021 and 16.7% in 2020. IPnest has released the “Design IP Report” in April 2023, ranking IP vendors by category (CPU, DSP, GPU & ISP, Wired Interface, SRAM Memory Compiler, Flash Memory Compiler, Library and I/O, AMS, Wireless… Read More
S2C Helps Client to Achieve High-Performance Secure GPU Chip Verification
S2C, a leading provider of FPGA-based prototyping solutions, has helped a client achieve high-performance secure GPU chip verification. With the help of S2C’s Prodigy prototyping solution, the client was able to start software development and hardware-software co-design early, leading to accelerated time-to-market… Read More
What’s New with Cadence Virtuoso?
It was back in 1991 that Cadence first announced the Virtuoso product name, and here we are 32 years later and the product is alive and doing quite well. Steven Lewis from Cadence gave me an update on something new that they call Virtuoso Studio, and it’s all about custom IC design for the real world. In those 32 years we’ve… Read More
Electronics Production in Decline
Shipments of PCs and smartphones were weak in 2022 and continue to decline in 2023. For the first quarter of 2023, IDC estimated PC shipments dropped 29% from a year earlier. This follows a 28% year-to-year decline in 4Q 2022. For the year 2022, PC shipments declined 16% from 2021, the largest year-to-year decline in the history of… Read More
Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More
Can Attenuated Phase-Shift Masks Work For EUV?
Normalized image log-slope (NILS) is probably the single most essential metric for describing lithographic image quality. It is defined as the slope of the log of intensity, multiplied by the linewidth [1], NILS = d(log I)/dx * w = w/I dI/dx. Essentially, it gives the % change in width for a given % change in dose. This is particularly… Read More
Podcast EP155: How User Experience design accelerates time-to-market and drives design wins
Dan is joined by Matt Genovese. Matt founded Planorama Design, a user experience design professional services company to design complex, technical software and systems that are simple and intuitive to use while reducing internal development and support costs. Staffed with seasoned engineers and user experience designers,… Read More
Moving Beyond RTL at #62DAC